Solid-State Devices TRIZ Cases

Vertical protrusions bridge deep defective pixels in organic EL displays, bypassing laser irradiation limits.

A semiconductor device structure uses impurity regions to form PN junctions within the substrate beneath stacked conductive layers.

A nitride semiconductor light emitting device integrates a nano light emitting diode array to boost optical extraction efficiency.

A resistive random access memory array uses spatially varying diffusion barrier layers to tailor oxygen ion dynamics across distinct regions.

A thin film transistor substrate uses dual gate insulator thicknesses to form high pressure resistance and low voltage transistors.

Acidic gas etching modifies coated glazing surfaces to enhance light scattering, resolving device complexity trade-offs in LEDs and PV modules.

A semiconductor ESD protection structure uses a field plate on an oxide layer to adjust trigger voltage via avalanche breakdown.

An etching stop layer between stacked structures guides vertical channel pillar alignment, preventing misalignment damage while increasing integration density.

Metallic bit-line pillars in 3D NOR-P memory devices reduce power consumption by shortening wire lengths while maintaining high write speeds.

A liquid crystal display uses indentation pattern parts in a light-shielding member to coordinate control forces on liquid crystal molecules.

Transistor partitioning in monolithic 3D flip-flops keeps clock circuits on one tier, reducing skew and improving timing margins.

Two-step dry etching process reduces contact hole width to 10 micrometers or less in thin film transistor array panels.

A PIN diode memory architecture uses an intrinsic semiconductor region to reduce leakage currents in compact storage cells.

Voltage differences create electric fields that guide micro devices to the receiving substrate, resolving alignment shifts during transfer.

A semiconductor light emitting device integrates a rectifying element below the light emitting unit to provide reverse overvoltage protection.

A moisture retaining film covers the light emitting region to store water vapor within the sealed panel structure.

Routing sensing lines underneath the encapsulation layer reduces non-display region area, enabling flexible bending without sacrificing touch sensing precision.

Electroless plating deposits a cobalt-tungsten-boron barrier on contact areas to prevent undercutting and oxidation during copper interconnect formation.

A solder bump couples a MEMS package body to a PCB blind pad, shifting resonance frequencies away from critical operational ranges.

Dynamic back-gate biasing reduces on-state resistance and leakage current without adding external bias generators.

A stacked semiconductor circuit uses a master chip with SRAM to repair failed memory cells on a slave chip.

Segmenting the device isolation layer into distinct thicknesses prevents leakage currents and program disturbances in scaled FinFET nonvolatile memory devices.

An air gap spacer reduces parasitic capacitance between the gate stack and contact plug, preventing electrical shorts while maintaining surface planarity.

Multi-fin drain structures with isolation layers confine sneak current paths, enhancing reliability and driving current in RRAM cells.

A copper-nickel alloy seed layer forms on a cobalt barrier to prevent peeling between electroless plating layers.

A via structure embeds an optical channel within a conductive liner to enable simultaneous signal transmission.

A segmented light-emitting device uses distinct host-guest layers to boost optical resonance and luminance.

Opaque antenna carrier with transparent plastic voids creates a visible logo in contactless smartcards.

Direct die attach mounts LED chips to conductive islands, eliminating wire bonds that absorb light and constrain packaging density.

An exciplex host material with a lower singlet energy level than the guest material drives efficient Förster energy transfer in organic electroluminescent devices.

Segmented processing masks the logic region during high temperature NVM fabrication, preventing leakage in high-K metal gate transistors.

Position-based voltage compensation stabilizes touch detection sensitivity across varying environmental conditions and display areas.

Hydrogen-modified SiNx layers terminate interface energy levels, reducing sneak currents and preventing write disturb in crosspoint nonvolatile memories.

An asymmetric auxiliary fluid channel drives flow in a main microfluidic channel, protecting biological samples from damaging pressure and temperature impacts.

Positioning gate ends near parallel interconnects allows sub-resolution assist features, resolving process margin loss for deep sub-micron polysilicon lines.

Integrating a fluoranthene-macrocyclic compound with alkali metal materials reduces drive voltage while maintaining high luminance efficiency.

VFET-based ReRAM cells resolve DRAM retention limits by storing data as resistance states within a scalable CMOS-compatible structure.

A mask assembly with protruding portions blocks deposition material from transmissive areas during organic light-emitting display manufacturing.

Ion implantation creates etch-selective layers in shallow trench isolation to control coupling ratio and prevent dishing during planarization.

Vertical pixel electrodes and overlapping common voltage lines create storage capacitors that lower kick-back voltage while maintaining aperture ratio.

Inverting the deposition order prevents anode corrosion while maintaining a high aperture ratio for OLED displays.

A resistive memory cell uses a trench conductor to connect variable resistance elements on a semiconductor substrate.

Adjusting ion implantation conditions prevents large fault defects on thin films by positioning cutout portions away from separation initiation points.

A vertical nonvolatile memory channel uses a doped source region to enable Fowler-Nordheim tunneling erase operations.

A power control system generates multiple voltage rails to selectively boost operating voltages of 8T bit cells during read and write operations.

Dual microlens arrays bundle and converge LED light while a focused absorber reduces external reflection for better bright room contrast.

Integrated crossover metal layer connects LED units in series, eliminating external regulator circuits to boost AC/DC conversion efficiency.

Plasma etching through a sacrificial film creates deeper via holes while preventing dimensional deviation and dielectric constant increases.

A magnetic memory device uses spin-orbit torque to reverse magnetization in the free layer without external fields.

A silicon photocathode uses a boron layer to prevent substrate oxidation and facilitate electron emission.

A thin film transistor substrate integrates capacitor electrodes with interconnections using shared material layers to simplify manufacturing steps.

Zinc adhesion layers and deformable underfill absorb thermosonic pressure to prevent bond pad cracking while improving interconnect strength.

Top emission OLED device connects cathode to auxiliary electrode through a bank gap, eliminating an additional mask process and improving manufacturing yield.

A GaN light emitting device uses mesh trenches filled with conductive material to expose the N-type layer for uniform current distribution.

Segmented micro light emitting devices guide light independently to prevent mirror image formation while maintaining a thin profile.

A well capacity adjustment gate controls the potential of a doped well in an imaging pixel to manage photocharge storage.

A light-emitting display device uses a bank with increased surface roughness to isolate subpixel common layers.

Sidewall dielectric spacers prevent charge leakage from active areas into charge trapping layers, ensuring accurate logical state indication.

A silicone urethane methacrylate encapsulant composition blocks oxygen and moisture ingress while maintaining flexibility for organic electronic devices.

A zero tilt ion implantation process forms a P well within a semiconductor substrate to minimize lattice collision and residual stress.

Direct wafer bonding with electroplated conductive plugs resolves manufacturing complexity while maintaining electrical connection reliability.

A ring gate transistor surrounds a channel region on a planar substrate to modulate electrical current flow through the memory cell structure.

A transparent display device separates driving transistors and capacitors in non-transmissive areas to prevent short circuits.

Resistance-reduction wires connect to power drive lines via through holes, reducing voltage drop and improving brightness uniformity across the display.

A tandem OLED structure uses a microcavity to convert green and red light into blue emission.

A stress detection portion extends from outside the thin film encapsulation layer to overlap and contact it.

Carbon nanotube masking structures scatter trapped photons, overcoming internal reflection losses in high-refractive-index semiconductor layers.

A manufacturing method reduces contact resistance in solid state image pickup apparatuses by forming a compound layer on peripheral circuit regions.

Through-holes continuous with trenches in the lead segment stress concentration during cutting while improving resin adhesion and sulfur ingress protection.

An overlapping conductive pattern boosts the touch driving signal through capacitance, reducing delay and improving sensitivity.

Integrating etching and ashing in one apparatus eliminates repeated substrate transfers, reducing mechanical defects while maintaining process reliability.

Scanning electron microscopy distinguishes metallic carbon nanotubes by color contrast, enabling their removal to resolve purity issues in semiconductor layers.

Epitaxial lateral overgrowth defines vertical trenches through dielectric opening filling, bypassing photolithography resolution limits.

Shifting block placement aligns metal track plans, eliminating bidirectional routing patterns that increase on-die spacing penalties.

A semiconductor device uses light-transmitting electrodes in the pixel portion to increase the aperture ratio.

Nitrogen-bonded carborane host material balances charge injection to resolve luminous efficiency and driving stability trade-offs.

Merging the light emitting unit and electrostatic protection unit into a single structure improves ESD immunity while controlling device complexity.

An intermediate fullerene layer reduces interface defects and carrier recombination in tin perovskite solar cells to enhance open voltage.

A fluorine-based polymer thin film sits between source/drain electrodes and the organic semiconductor layer in an organic thin film transistor.

Thermal treatment forms cambered surfaces on the substrate backside to improve photo-electric conversion efficiency and sensitivity.

Asymmetric bump connection vias bridge vertical semiconductor channels to bit lines in 3D memory stacks.

Optimized spherical lens curvature maintains high packaging density while ensuring sufficient cumulative illuminance during scanning operations.

Vertical conductive pillars replace buried bit lines to lower resistance and mitigate short channel effects.

A stacked neuromorphic device uses through silicon vias to connect logic and core dies, enabling efficient weight storage and calculation within neural networks.

A display substrate uses a sub-trench and opening portion to form thicker gate lines that reduce signal resistance.

A semiconductor apparatus uses a channel selection unit to dynamically select pseudo channels within core chips.

Pendant polycyclic aromatic precursors attached to polymer chains resolve low viscosity issues, enabling repeatable and uniform thin film coatings.

Partial scribe line cutting blocks adhesive spillage to maintain wafer positioning accuracy and increase transfer success rates for micro-LED displays.

Monoclinic hafnium or zirconium oxide dielectrics with controlled hydrogen concentration minimize leak current in image sensor capacitors.

PECVD deposition of amorphous silicon at low temperatures prevents CMOS heat damage while achieving electrical conductivity and minimal mechanical stress.

Alternating groove patterns on a substrate guide hole transport solution to prevent non-uniform drying and ensure consistent light emission characteristics.

Parallel treatment chambers eliminate sequential bottlenecks, enabling flexible layer structure changes without reconstruction.

Expanding tape allows simultaneous bonding of LED elements to reduce individual placement time and boost manufacturing efficiency.

A single crystalline AlGaN buffer layer enables two-dimensional epitaxial growth on mismatched substrates.

Distinct exposure steps for silicon display and peripheral regions prevent splicing alignment errors, improving yield and brightness uniformity.

Epitaxial growth aligns crystal lattices between memory elements and transistors, reducing cell-to-cell variations.

A processing system uses periodic reset signals to drive high-pass filtering, rejecting slow ambient light interference while preserving detection accuracy.

Metal layers reinforce adhesion between substrates and encapsulation portions, reducing dead space while maintaining structural strength.