Solid-State Devices TRIZ Cases

Vertical protrusions bridge deep defective pixels in organic EL displays, bypassing laser irradiation limits.

A semiconductor device structure uses impurity regions to form PN junctions within the substrate beneath stacked conductive layers.

A nitride semiconductor light emitting device integrates a nano light emitting diode array to boost optical extraction efficiency.

A resistive random access memory array uses spatially varying diffusion barrier layers to tailor oxygen ion dynamics across distinct regions.

A thin film transistor substrate uses dual gate insulator thicknesses to form high pressure resistance and low voltage transistors.

Acidic gas etching modifies coated glazing surfaces to enhance light scattering, resolving device complexity trade-offs in LEDs and PV modules.

A semiconductor ESD protection structure uses a field plate on an oxide layer to adjust trigger voltage via avalanche breakdown.

An etching stop layer between stacked structures guides vertical channel pillar alignment, preventing misalignment damage while increasing integration density.

Metallic bit-line pillars in 3D NOR-P memory devices reduce power consumption by shortening wire lengths while maintaining high write speeds.

A liquid crystal display uses indentation pattern parts in a light-shielding member to coordinate control forces on liquid crystal molecules.

Transistor partitioning in monolithic 3D flip-flops keeps clock circuits on one tier, reducing skew and improving timing margins.

Two-step dry etching process reduces contact hole width to 10 micrometers or less in thin film transistor array panels.

A PIN diode memory architecture uses an intrinsic semiconductor region to reduce leakage currents in compact storage cells.

Voltage differences create electric fields that guide micro devices to the receiving substrate, resolving alignment shifts during transfer.

A semiconductor light emitting device integrates a rectifying element below the light emitting unit to provide reverse overvoltage protection.

A moisture retaining film covers the light emitting region to store water vapor within the sealed panel structure.

Routing sensing lines underneath the encapsulation layer reduces non-display region area, enabling flexible bending without sacrificing touch sensing precision.

Electroless plating deposits a cobalt-tungsten-boron barrier on contact areas to prevent undercutting and oxidation during copper interconnect formation.

A solder bump couples a MEMS package body to a PCB blind pad, shifting resonance frequencies away from critical operational ranges.

Dynamic back-gate biasing reduces on-state resistance and leakage current without adding external bias generators.

A stacked semiconductor circuit uses a master chip with SRAM to repair failed memory cells on a slave chip.

Segmenting the device isolation layer into distinct thicknesses prevents leakage currents and program disturbances in scaled FinFET nonvolatile memory devices.

An air gap spacer reduces parasitic capacitance between the gate stack and contact plug, preventing electrical shorts while maintaining surface planarity.

Multi-fin drain structures with isolation layers confine sneak current paths, enhancing reliability and driving current in RRAM cells.

A copper-nickel alloy seed layer forms on a cobalt barrier to prevent peeling between electroless plating layers.

A via structure embeds an optical channel within a conductive liner to enable simultaneous signal transmission.

A segmented light-emitting device uses distinct host-guest layers to boost optical resonance and luminance.

Opaque antenna carrier with transparent plastic voids creates a visible logo in contactless smartcards.

Direct die attach mounts LED chips to conductive islands, eliminating wire bonds that absorb light and constrain packaging density.

An exciplex host material with a lower singlet energy level than the guest material drives efficient Förster energy transfer in organic electroluminescent devices.

Segmented processing masks the logic region during high temperature NVM fabrication, preventing leakage in high-K metal gate transistors.

Position-based voltage compensation stabilizes touch detection sensitivity across varying environmental conditions and display areas.

Hydrogen-modified SiNx layers terminate interface energy levels, reducing sneak currents and preventing write disturb in crosspoint nonvolatile memories.

An asymmetric auxiliary fluid channel drives flow in a main microfluidic channel, protecting biological samples from damaging pressure and temperature impacts.

Positioning gate ends near parallel interconnects allows sub-resolution assist features, resolving process margin loss for deep sub-micron polysilicon lines.

Integrating a fluoranthene-macrocyclic compound with alkali metal materials reduces drive voltage while maintaining high luminance efficiency.

VFET-based ReRAM cells resolve DRAM retention limits by storing data as resistance states within a scalable CMOS-compatible structure.

A mask assembly with protruding portions blocks deposition material from transmissive areas during organic light-emitting display manufacturing.

Ion implantation creates etch-selective layers in shallow trench isolation to control coupling ratio and prevent dishing during planarization.

Vertical pixel electrodes and overlapping common voltage lines create storage capacitors that lower kick-back voltage while maintaining aperture ratio.

Inverting the deposition order prevents anode corrosion while maintaining a high aperture ratio for OLED displays.

A resistive memory cell uses a trench conductor to connect variable resistance elements on a semiconductor substrate.

Adjusting ion implantation conditions prevents large fault defects on thin films by positioning cutout portions away from separation initiation points.

A vertical nonvolatile memory channel uses a doped source region to enable Fowler-Nordheim tunneling erase operations.

A power control system generates multiple voltage rails to selectively boost operating voltages of 8T bit cells during read and write operations.

Dual microlens arrays bundle and converge LED light while a focused absorber reduces external reflection for better bright room contrast.

Integrated crossover metal layer connects LED units in series, eliminating external regulator circuits to boost AC/DC conversion efficiency.

Plasma etching through a sacrificial film creates deeper via holes while preventing dimensional deviation and dielectric constant increases.