Vertical FET ReRAM Cell Integration for CMOS Compatibility

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The scaling of dynamic random access memory (DRAM) technology is facing challenges due to retention time issues, necessitating the development of new memory technologies, with emerging memory devices like phase change memory (PCM), magnetic random access memory (MRAM), and resistive random access memory (ReRAM) storing data as resistance values.

Innovation Solution

The formation of on-chip resistive memory using vertical field-effect transistors (VFETs) and resistive elements, arranged in columns and rows to create resistive random access memory (ReRAM) cells, where each VFET and resistive element pair forms a memory cell with the top source/drain regions acting as bottom contacts for the resistive elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM technology is scaled down to increase memory density, then memory capacity increases, but retention time deteriorates

Engineering Contradiction:

Improvememory densityVSAvoidretention time

Core Design Contradiction:

Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The patent transitions from DRAM to emerging memory technologies (PCM, MRAM, STT-MRAM, ReRAM) that store data as resistance values rather than charge, fundamentally changing the storage parameter from electrical charge to resistance state. This parameter change enables non-volatile storage with improved retention time while maintaining scalability for high memory density

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the charge-based storage mechanism of DRAM with resistance-based storage mechanisms in emerging memory devices. Specifically, ReRAM uses variations in resistance values to store data, substituting the mechanical/electrical charge system with a resistance-based system that provides non-volatile storage capability

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Ease of manufacture

If emerging memory devices are integrated with CMOS processes, then compatibility and manufacturability improve, but device structure complexity increases

Engineering Contradiction:

ImproveCMOS process compatibilityVSAvoidmemory cell structure

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The memory cell is segmented into distinct functional components: a transistor for control and a separate resistive element for data storage. This segmentation allows the resistive element to be integrated with standard CMOS transistors while maintaining clear functional separation, improving manufacturability through modular integration

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The resistive element serves multiple functions: it acts as both the storage medium (storing data as resistance states) and integrates with the transistor to form a complete memory cell. This multi-functionality reduces the need for additional dedicated components, simplifying the overall integration process with CMOS processes

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the integration of ReRAM with CMOS processes, providing efficient and scalable non-volatile memory solutions suitable for system-on-chip applications, addressing the limitations of DRAM technology.

Implementation Method 1

forming a plurality of vertical field-effect transistors (VFETs) disposed on a substrate... each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region and wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate

Methodology Applied

Scientific EffectField-effect transistor operation: Electric Field

Implementation Method 2

Emerging memory devices store data as resistance values... resistive random access memory (ReRAM or RRAM) use variations of resistance values to store data

Methodology Applied

Scientific EffectElectrical resistance: Electrical Resistance

Data Source

PatentUS10522594B2Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element

Publication Date: 2019.12.31 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method of forming a semiconductor structure includes forming a plurality of vertical field-effect transistors (VFETs) disposed on a substrate and forming a plurality of resistive elements disposed over top surfaces of the VFETs. Each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell. The VFETs are arranged in two or more columns and two or more rows, wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region and wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate. Top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs.