PIN Diode Memory Architecture Reducing Leakage Current
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Solution Overview
Problem
Conventional memory architectures face challenges in efficiently accessing and storing logic states due to the limitations of select devices, such as conventional PN diodes, which have high footprints and abrupt junctions leading to lower breakdown voltages and increased leakage currents.
Innovation Solution
The use of semiconductor PIN diodes with non-intrinsic p-type and n-type regions and an intrinsic region positioned between them, acting as a select device for memory cells, reduces the footprint and increases breakdown voltage by incorporating a buried bit/word line and intrinsic semiconductor region, allowing for efficient signal transmission and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional PN diodes are used as select devices, then the device structure is simple, but the footprint area is large and leakage current is high
Solution Approach 1:
The patent transitions from a planar PN diode structure to a vertical PIN diode structure that extends into the third dimension. The intrinsic region is positioned between the p-type and n-type regions in a vertical configuration, allowing the select device to achieve compact lateral footprint while maintaining sufficient breakdown voltage through increased vertical depth. This dimensional change resolves the contradiction between simple structure and compact area.
2Device complexity
If conventional PN diodes are used as select devices, then the device structure is simple, but the breakdown voltage is low
Solution Approach 1:
The patent employs a composite semiconductor structure combining three distinct regions: p-type semiconductor material, intrinsic semiconductor material, and n-type semiconductor material. This PIN composite structure leverages the unique properties of each material layer to achieve high breakdown voltage. The intrinsic region acts as a high-resistivity buffer that withstands high reverse voltages, while the doped regions provide efficient carrier injection, resolving the contradiction between structural simplicity and high breakdown voltage capability.
3Ease of manufacture
If conventional PN diodes are used as select devices, then manufacturing is straightforward, but leakage current is increased
Solution Approach 1:
The patent applies local quality by creating distinct regions with different semiconductor properties within the diode structure. The intrinsic region is specifically engineered with very low doping concentration to provide high resistivity and minimize leakage current in the depletion region. Meanwhile, the p-type and n-type regions maintain appropriate doping levels for efficient forward conduction. This localized differentiation of material properties reduces leakage current while preserving manufacturability through standard semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PIN diode configuration enhances memory cell access and storage efficiency by reducing leakage currents and increasing breakdown voltage, enabling more reliable and compact memory architectures.
Implementation Method 1
an intrinsic region positioned between the non-intrinsic region and the portion of the bit/word line
Implementation Method 2
increases breakdown voltage by incorporating a buried bit/word line and intrinsic semiconductor region
Data Source
AI summary
A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.