Stacked Semiconductor Circuit Memory Repair via Master-Slave SRAM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor integrated circuits, the inefficient increase in master chip size to connect with slave chips through TSVs leads to a reduction in net die and additional time for repair operations, causing asynchronous parameters to increase due to the lack of memory in the master chip and the presence of normal and redundant cells in the slave chip.
Innovation Solution
A semiconductor integrated circuit structure where a master chip with SRAM memory areas is stacked with slave chips having DRAM memory areas, allowing for equal chip sizes and enabling the master to determine and replace failed memory cells using redundant cells, thereby preventing activation of failed memory cells during refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the master chip size is increased to connect with slave chips through TSVs, then the connection capability is improved, but the net die is reduced
Solution Approach 1:
The patent transitions from a single-plane chip layout to a three-dimensional stacked architecture. By placing the master chip and slave chip in different vertical layers and connecting them through TSVs, the design achieves improved connection capability without reducing the net die area of individual chips. This dimensional transition allows both chips to maintain their full area potential while enabling inter-chip communication.
2Reliability
If repair operations are performed in the slave chip with normal and redundant cells, then the repair capability is improved, but the operation time increases causing asynchronous parameters to increase
Solution Approach 1:
The patent merges the repair functionality into the master chip by providing SRAM memory areas that can serve as backup storage. When a failure is detected in the slave chip's DRAM, the master chip's SRAM can take over the repair operation, eliminating the need for separate repair circuits in the slave chip and reducing overall operation time.
Solution Approach 2:
The master chip performs preliminary detection of failures in the slave chip's memory cells. By detecting and initiating repair operations proactively before they affect system performance, the patent minimizes the time loss associated with repair operations and reduces asynchronous parameters.
3Device complexity
If the master chip has no memory area, then the circuit complexity is reduced, but the repair operation efficiency is worsened
Solution Approach 1:
The master chip is designed with SRAM memory areas that serve multiple functions: storing data, performing repair operations, and providing backup storage. This multi-functionality allows the master chip to efficiently handle repair operations without significantly increasing circuit complexity, as the same memory structure serves multiple purposes.
Data Source
AI summary
A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.