3D Non-Volatile Memory Stack With Impurity Regions
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Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, leading to the development of three-dimensional non-volatile memory devices with stacked memory cells, but existing structures face challenges in operational reliability and manufacturing complexity.
Innovation Solution
A semiconductor device structure featuring a stack of conductive and insulating layers with impurity regions and trenches, where the substrate has a different impurity type, forming PN junctions to prevent current loss and enhance reliability, and a manufacturing method involving impurity region formation and trench creation to simplify the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional non-volatile memory devices are adopted to improve integration density, then storage capacity increases, but manufacturing complexity and operational reliability challenges arise
Solution Approach 1:
The substrate is divided into multiple impurity regions with different impurity types (first type and second type) arranged in a specific pattern. This segmentation allows different regions to serve different functional purposes, enabling simplified manufacturing processes while maintaining high integration density in the three-dimensional memory structure.
Solution Approach 2:
Different impurity regions are introduced at specific locations within the substrate to create localized electrical characteristics. The first impurity regions and second impurity regions are positioned to form PN junctions at critical interfaces, providing tailored electrical properties where needed without complicating the overall manufacturing process.
2Quantity of substance
If complex stack structures with multiple layers are used to increase memory capacity, then integration density improves, but current loss and operational reliability deteriorate
Solution Approach 1:
Impurity regions are pre-formed in the substrate before stacking the conductive and insulating layers. These preliminary impurity regions create PN junctions that proactively prevent current loss and leakage before the memory device operates, thereby improving operational reliability without adding complexity to the stack structure itself.
Solution Approach 2:
The PN junctions formed by the impurity regions convert potential harmful current leakage into beneficial current confinement. The junctions redirect and control current flow paths, transforming what would be loss into controlled electrical behavior that enhances device reliability and performance.
3Ease of manufacture
If traditional two-dimensional memory structures are used, then manufacturing processes remain simple, but integration density is limited
Solution Approach 1:
The invention transitions from traditional two-dimensional memory cell arrangements to a three-dimensional structure where conductive layers and insulating layers are stacked vertically. This dimensional change dramatically increases integration density while the impurity region configuration in the substrate maintains compatibility with simplified manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure and method improve the reliability and integration density of three-dimensional non-volatile memory devices by stabilizing current flow and simplifying the manufacturing process, addressing the limitations of two-dimensional devices.
Implementation Method 1
A semiconductor device may include stack structures each including a first conductive layer including a first type impurity, a substrate disposed under the stack structures and including a second type impurity different from the first type impurity, first impurity regions disposed in the substrate and including the first type impurity
Data Source
AI summary
A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.