Polysilicon Interconnect Layout for Photolithography Process Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit manufacturing, the photolithography process faces challenges in maintaining resolution and critical dimension control for polysilicon interconnects that extend over isolation structures and run perpendicular to the preferred orientation, leading to reduced process margin and increased chip area.
Innovation Solution
The layout of gate-level elements is constrained such that the ends of gate-level lines are positioned either within a specific distance or far enough from interconnects to allow for the placement of sub-resolution assist features, maintaining photolithography process margin without modifying the fabrication process or increasing chip area, and ensuring compatibility with off-axis illumination photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If polysilicon interconnects are extended over isolation structures perpendicular to the preferred orientation, then interconnect routing flexibility is improved, but photolithography process margin deteriorates
Solution Approach 1:
The patent applies different layout constraints to different regions of the circuit. Specifically, it constrains the spacing between gate-level lines and interconnects in local areas where photolithography process margin is compromised, while allowing broader routing flexibility in other regions. This localized constraint approach maintains overall routing versatility while protecting critical areas from manufacturing defects.
2Manufacturing precision
If layout constraints are imposed on gate-level lines, then photolithography process margin is improved, but design flexibility deteriorates
Solution Approach 1:
The patent segments the layout constraints into specific, manageable rules: (1) minimum spacing between gate-level lines and interconnects, and (2) maximum spacing to prevent excessive isolation oxide coverage. These segmented constraints are easier to implement and verify than comprehensive layout restrictions, reducing the perceived complexity while maintaining manufacturing precision.
3Area of stationary object
If gate-level lines are positioned close to interconnects, then chip area is minimized, but photolithography resolution deteriorates
Solution Approach 1:
The patent changes the spacing parameter between gate-level lines and interconnects to optimal values that balance area minimization and photolithography resolution. By establishing specific minimum and maximum spacing ranges, the patent identifies parameter zones where both compact layout and manufacturing precision are achieved simultaneously, rather than treating them as strictly opposing goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the photolithographic process margin for interconnects over isolation oxide structures, maintaining resolution and dimensional control while minimizing chip area and adhering to existing photolithography processes, even for features in the deep sub-micron range.
Implementation Method 1
an SRAF that is properly spaced from a true critical dimension feature (i.e., one that is intended to be printed) provides a diffraction effect similar to an adjacent full-width feature, resulting in proper focus of the desired critical dimension feature
Implementation Method 2
This illumination enables higher order pattern information to be projected onto the image plane (i.e., the surface of the photoresist) than would otherwise result from incident light normal to the mask plane
Data Source
AI summary
A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.