RRAM Multi-Fin Drain Structure for Sneak Current Reduction
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Solution Overview
Problem
Resistive random access memory (RRAM) devices with a 1T1R structure face reliability issues due to sneak current interference between resistors connected to the same transistor, compromising device performance.
Innovation Solution
The RRAM device incorporates a multi-fin drain region with isolation layers between semiconductor fins, reducing sneak current by creating a longer conductive path and using a gate structure that wraps around the fins, along with lightly and heavily doped regions to confine sneak current, and contacts with slanted edges to improve current collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two resistors are connected to the same transistor to increase capacity, then the cell size is decreased, but sneak current flows between the resistors compromising reliability
Solution Approach 1:
The drain region is segmented into multiple semiconductor fins separated by isolation layers, creating distinct current paths for each RRAM unit. This segmentation prevents sneak current from flowing between adjacent RRAM units while maintaining the increased storage capacity of the 1TNR structure.
Solution Approach 2:
Isolation layers are introduced as intermediary structures between adjacent semiconductor fins. These isolation layers act as barriers that block sneak current paths between RRAM units connected to the same transistor, thereby improving device reliability without reducing storage capacity.
2Reliability
If the conductive path is lengthened to reduce sneak current, then the resistance increases, but the driving current decreases
Solution Approach 1:
Different regions of the device are doped with different concentrations: lightly doped regions are used where high resistance is needed to block sneak current, while heavily doped regions are used where low resistance is needed to ensure sufficient driving current. This local quality variation allows simultaneous optimization of both sneak current reduction and driving current maintenance.
Solution Approach 2:
The drain region is structured as multiple vertical fins instead of a planar region, extending the conductive path in the vertical dimension. This dimensional change increases the path length for sneak current while maintaining compact lateral footprint, and combined with selective doping, allows control over resistance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces sneak current and enhances the performance of RRAM devices by increasing resistance and improving driving current, thereby improving the reliability and efficiency of the memory cells.
Implementation Method 1
The semiconductor fins are separated from each other by an isolation layer
Implementation Method 2
using a gate structure that wraps around the fins, along with lightly and heavily doped regions to confine sneak current
Data Source
AI summary
A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.