8T Bit-Cell Voltage Boosting for Low-Voltage Operation
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Solution Overview
Problem
Integrated circuits face challenges in operating efficiently at low voltages due to variations in die-to-die and within-die process parameters, leading to higher power consumption and reduced performance, especially in 8T bit-cell arrays and other logic blocks.
Innovation Solution
A power control system that provides a multi-Vcc environment by generating multiple voltage rails, including Vcc1 and Vcc2, and using level-shifted controls to selectively boost the operating voltage of bit cells during read and write operations, allowing for improved energy efficiency and reduced contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger-size devices are used for read and write ports to mitigate process parameter variations, then the circuits can operate at low voltage, but the power consumption increases at high performance mode with higher switching capacitance
Solution Approach 1:
The register file is divided into multiple groups, with each group having its own power supply voltage that can be independently controlled. This allows different parts of the register file to operate at different voltages, enabling low voltage operation for reliability while managing power consumption through selective voltage application to active groups.
Solution Approach 2:
The power supply voltage for each register file group is made dynamically adjustable based on operational requirements. The system can transition between different voltage states (e.g., first voltage for low power, second voltage for high performance), allowing the circuit to adapt its power consumption characteristics to match actual operational needs rather than being fixed at a single voltage level.
2Reliability
If larger-size devices are used for read and write ports, then process parameter variations are mitigated, but switching capacitance increases leading to higher power at high performance mode
Solution Approach 1:
By segmenting the register file into multiple groups with independent power supplies, the system can apply larger devices only to groups that require high performance operations, while keeping other groups at lower voltages with smaller devices, thus mitigating process variations where needed without universally increasing power consumption.
Solution Approach 2:
The system dynamically changes the voltage parameter supplied to different register file groups based on operational mode. At high performance mode, voltage is increased to allow larger devices to operate efficiently with higher switching capacitance, while at lower performance modes, voltage is reduced to minimize power consumption, effectively managing the trade-off between stability and power.
Data Source
AI summary
Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.