Flash Memory STI Etch Control via Ion Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for a method to form memory arrays with low aspect ratio STI structures and high coupling ratio between floating gates and control gates, while maintaining uniform control of the coupling ratio and preventing dishing in peripheral areas during planarization.
Innovation Solution
The method involves forming gate dielectric layers and a first floating gate layer, depositing a Silicon Nitride layer, creating STI trenches, filling them with oxide, and selectively removing implanted STI material to control the etch depth, along with using protrusions and soft etching to achieve a planar surface across both memory and peripheral areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate is made thicker to increase coupling area, then the coupling ratio between floating gate and control gate is improved, but the aspect ratio of STI structures increases making them difficult to fill
Solution Approach 1:
The patent divides the STI filling process into multiple stages: first filling the trench with dielectric material, then performing selective removal of portions of the STI structure using implantation and etching. This segmentation allows the floating gate to be made thicker for better coupling while the STI aspect ratio is effectively reduced through selective removal, resolving the contradiction between coupling ratio and fill quality
Solution Approach 2:
The patent performs preliminary implantation of ions into the STI structure before the final etching step. This preliminary action modifies the STI material properties in specific regions, enabling subsequent selective removal of portions of the STI structure. This allows the floating gate to be formed with greater thickness for improved coupling while maintaining manufacturability through controlled STI removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved control over the coupling ratio between floating and control gates, ensures uniformity, and prevents dishing in peripheral structures, resulting in a more accurate and efficient planarization process.
Implementation Method 1
ions are implanted through the conductive polysilicon into the underlying STI structures
Implementation Method 2
The polysilicon is then removed down to the level of the top surface of the STI structures
Implementation Method 3
The implanted STI is then etched away
Data Source
AI summary
A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.