NVM Cell and Logic Transistor Integration via Segmented Processing
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Solution Overview
Problem
The integration of non-volatile memory (NVM) cells with logic transistors is challenging due to different requirements, particularly with high k gate dielectrics and metal gates, which cannot withstand high temperatures and result in leakage issues from exposed transistor regions.
Innovation Solution
A method is developed where the gate structure of the NVM cell is formed with a charge storage layer while masking the logic region, allowing for the formation of a well in the logic transistor after removing the polysilicon layer, enabling the integration of NVM cells and logic transistors on the same integrated circuit without degrading the performance of logic transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high k gate dielectrics are used in logic transistors, then leakage is reduced, but they cannot withstand the high temperatures required for NVM cell fabrication
Solution Approach 1:
The integrated circuit is divided into distinct NVM region and logic region with separate processing sequences. The NVM region undergoes high-temperature processing first to form charge storage layers, while the logic region is masked and protected during this phase. After NVM fabrication, the logic region is unmapped and processed at lower temperatures appropriate for high k gate dielectrics.
Solution Approach 2:
The NVM cell structures including charge storage layers are formed in advance before the logic transistor fabrication. This preliminary action allows the NVM region to be established with its required high-temperature processed layers before introducing the temperature-sensitive logic region structures.
2Manufacturing precision
If thick oxide layers are etched for high voltage transistors, then gate dielectric thickness is reduced, but isolation oxide recess exposes sidewall surfaces causing threshold voltage control issues and leakage
Solution Approach 1:
A mandrel structure is formed on the sidewalls of the gate structure before oxide etching. This mandrel prevents the etch from recessing the isolation oxide below the gate structure level, thereby preventing exposure of the transistor channel region sidewall surfaces that would cause threshold voltage control issues and leakage.
Solution Approach 2:
The mandrel acts as an intermediary protective element during the oxide etching process. It temporarily occupies the space that would otherwise allow over-etching, and is removed after the etching is complete, having served its protective function.
3Adaptability or versatility
If NVM cells are integrated with logic transistors, then circuit functionality is enhanced, but the different processing requirements make integration difficult
Solution Approach 1:
The integrated circuit is divided into distinct NVM region and logic region with separate processing sequences. The NVM region undergoes high-temperature processing first to form charge storage layers, while the logic region is masked and protected during this phase. After NVM fabrication, the logic region is unmapped and processed at lower temperatures appropriate for high k gate dielectrics.
Solution Approach 2:
The NVM cell structures including charge storage layers are formed in advance before the logic transistor fabrication. This preliminary action allows the NVM region to be established with its required high-temperature processed layers before introducing the temperature-sensitive logic region structures.
Data Source
AI summary
A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region.