FinFET Insulating Layer Segmentation for Leakage Control
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Solution Overview
Problem
Conventional transistors with horizontal channel structures face challenges in scaling down due to short channel effects and drain-induced barrier lower (DIBL) effects, leading to increased variability and difficulty in controlling transistor states, especially when channel lengths are reduced below 30 nm, and nonvolatile memory devices experience program disturbances due to leakage currents caused by thin device isolation layers.
Innovation Solution
The implementation of fin field effect transistors (FinFETs) with an insulating layer between the fins and the substrate, where the insulating layer is directly connected to the device isolation layer and has a different thickness, effectively isolating adjacent fins and reducing program disturbances by preventing leakage currents, allowing for independent operation and improved control over transistor states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the device isolation layer is made thinner to reduce manufacturing complexity and cost, then manufacturing precision is improved, but leakage current increases causing program disturbance
Solution Approach 1:
The device isolation structure is segmented into two distinct layers: a first device isolation layer and a second device isolation layer. This segmentation allows each layer to have different thicknesses and functions, with the first layer providing electrical isolation and the second layer providing mechanical support and stress control, thereby preventing leakage current while maintaining manufacturing feasibility
Solution Approach 2:
Different regions of the isolation structure have different thicknesses tailored to their specific functions. The first device isolation layer has a thickness optimized for electrical isolation properties, while the second device isolation layer has a different thickness optimized for mechanical support. This local quality approach ensures that each part of the structure performs its intended function effectively
2Productivity
If the channel length is reduced to scale down transistor size, then device integration density is improved, but short channel effects and DIBL effects increase
Solution Approach 1:
The patent transitions from a conventional planar transistor structure to a FinFET structure that utilizes three-dimensional vertical channels. By forming fins that extend vertically from the substrate and applying gate electrodes that wrap around these fins, the design moves from two-dimensional planar geometry to three-dimensional vertical geometry, enabling effective channel control at scaled dimensions
Solution Approach 2:
The gate electrode is configured to wrap around the fin structure in a nested arrangement, with the gate encompassing the channel region from multiple sides. This nested configuration allows the gate to exert control over the channel from top, bottom, and sidewalls, providing superior electrostatic control compared to conventional top-only gating
3Object-generated harmful factors
If the device isolation layer is made thicker to prevent leakage current, then program disturbance is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The isolation structure is divided into two separate device isolation layers that can be formed using standard manufacturing processes. This segmentation allows the total isolation thickness to be achieved without requiring a single excessively thick layer, maintaining compatibility with existing fabrication techniques while providing sufficient electrical isolation
Solution Approach 2:
The first device isolation layer is formed prior to fin formation, establishing the electrical isolation foundation before the three-dimensional fin structures are created. This preliminary action ensures that isolation is built into the structure from the beginning of the fabrication sequence, preventing leakage current before it can occur
Data Source
AI summary
A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device isolation layer and has a different thickness than the device isolation layer. A gate electrode crosses over the fin. A gate insulating layer is between the gate electrode and the fin. Source and drain regions are on the fins and on opposite sides of the gate electrode. Related nonvolatile memory devices that include FinFETs and methods of making FinFETs and nonvolatile memory devices are also disclosed.