Compact Resistive Memory Cell With Trench Conductor
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Solution Overview
Problem
Current resistive memory cell designs occupy significant substrate area, limiting further miniaturization and efficiency in memory storage.
Innovation Solution
The memory cell design incorporates a selection transistor with a control gate and a variable-resistance element formed in a trench on a semiconductor substrate, sharing conduction regions and using a trench conductor to connect multiple memory cells, reducing substrate area while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional memory cell structure is used, then functionality is maintained, but substrate area occupied is large
Solution Approach 1:
The patent merges the bit line and word line into a single gate structure that serves dual purposes. The gate electrode functions as both the control gate for the selection transistor and as the bit line for data access, eliminating the need for separate bit line routing and reducing overall cell area.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional structure by forming the variable resistance element vertically within the substrate. This vertical integration allows the cell to occupy less lateral substrate area while maintaining all necessary functional components.
2Quantity of substance
If substrate area is reduced, then storage density increases, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode structure serves multiple functions simultaneously - as control gate, as bit line, and as a reference for variable resistance element formation. This self-service approach reduces the number of separate manufacturing steps and alignment requirements, thereby reducing precision demands despite compact dimensions.
Solution Approach 2:
The selection transistor's gate electrode is designed to perform multiple functions: controlling the selection transistor operation and serving as the bit line for the memory cell. This multi-functionality reduces the total component count and simplifies the manufacturing process, lowering precision requirements.
Data Source
AI summary
The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.