3D Floating-Gate Multiple-Input Device for High-Density Neural Computing
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Solution Overview
Problem
Conventional majority gate weighted sum architectures are planar, leading to significant scaling and device electrostatic disadvantages, limiting device density and causing electrical interference challenges.
Innovation Solution
A 3D floating-gate multiple-input device is developed, utilizing a single transistor to replace multiple transistor and logic equivalent units, enabling die scaling and cost reduction, with a 3D nanowire device providing both majority gate operation and weighted-sum computation through capacitive coupling or electron tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar architectures are used for majority gate weighted sum computations, then device structure is simple and manufacturing is easier, but device density is limited and electrical interference occurs
Solution Approach 1:
The patent transitions from planar 2D architectures to three-dimensional vertical architectures. The nanowire channel extends vertically with gate electrodes positioned at different heights and angular orientations, enabling multiple inputs to be stacked in the vertical dimension rather than spread out planarly. This dimensional transition increases device density while maintaining manufacturability through standard semiconductor processing techniques adapted for 3D structures.
2Device complexity
If planar architectures are used for majority gate weighted sum computations, then device structure is simple, but electrical interference challenges arise
Solution Approach 1:
By moving to vertical 3D stacking, the patent spatially separates multiple input signals in the vertical dimension rather than having them co-planar. This vertical separation reduces capacitive coupling and electrical interference between input lines while maintaining compact footprint. The gate electrodes are positioned at different heights and angles, further isolating signal paths.
Solution Approach 2:
The patent implements a nested structure where gate electrodes are positioned concentrically around the vertical nanowire channel at different radial distances and angular positions. This nested arrangement allows multiple control gates to be integrated around a single channel, reducing the number of separate device instances needed and minimizing inter-device interference while maintaining individual gate control.
3Adaptability or versatility
If multiple transistor and logic equivalent units are used for weighted sum computations, then computational functionality is achieved, but die area is large and scaling is limited
Solution Approach 1:
The patent merges multiple transistor functions into a single vertical nanowire device structure. One nanowire channel with multiple gate electrodes replaces what would traditionally require multiple separate transistors and logic units. This consolidation achieves the same weighted sum computational functionality in a single compact device, dramatically reducing die area and enabling scaling.
Solution Approach 2:
The vertical nanowire device with multiple angularly-positioned gate electrodes serves multiple functions simultaneously: it performs weighted sum computations, implements majority logic, and can be configured for different computational operations by adjusting gate voltages. This multi-functionality eliminates the need for separate dedicated circuits for different logical operations, reducing overall die area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D floating-gate multiple-input device achieves improved device density and reduced electrical interference, enabling efficient weighted-sum computations and neural computing applications with dynamic reconfiguration capabilities.
Implementation Method 1
In either a capacitive coupling or a tunneling configuration, the gate has the capability to create an output that is a function of the weighted sums of the input voltages applied
Implementation Method 2
In either a capacitive coupling or a tunneling configuration, the gate has the capability to create an output that is a function of the weighted sums of the input voltages applied
Data Source
AI summary
A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.