Majority/Minority Circuits TRIZ Cases
- Memory Majority Detector Using Dual-Voltage Sense Amplification
Dual-voltage precharge and sensing cut transistor count and power use while preserving fast majority detection in memory circuits.
- Tristate Output Buffer Layout to Prevent Cross Currents
Independent series-controlled branches and majority voting prevent cross currents and radiation-induced voltage faults in tristate output buffers.
- Inline Spin-Wave Majority Gate Layout for Low-Loss Scaling
An inline waveguide layout lets spin-wave generators and detectors cut footprint and signal loss while improving majority gate scalability.
- Inline Spin Wave Majority Gate Layout for Compact Low-Loss Logic
A straight waveguide aligns spin wave generators and detectors to preserve interference while cutting area use and wave losses.
- Replica Logic Circuit Switching for BTI-Stable Low-Power States
A replica logic circuit compares transistor thresholds and switches static states to limit BTI drift and clock duty-cycle errors in low-power mode.
- Bitonic Sort Majority Circuit for Small-Area Vote Accuracy
A bitonic sort circuit replaces adder-heavy majority logic to keep area small while preserving accurate voting across larger input ranges.
- Self-Correcting Voting Latches for SEU-Resistant TMR Circuits
Pull-up and pull-down voting latches self-correct SEU errors in TMR circuits while cutting transistor count and improving programmable IC reliability.
- Redundant Circuit Voting Using Adder Carry for SEU Detection
Adder carry and XOR logic replace separate majority voters, cutting area and delay while detecting SEU-driven output mismatches.
- Redundant Memory Cell Voting for Radiation-Tolerant Arrays
Majority voting across redundant memory cells corrects radiation-induced bit flips while avoiding the power and complexity of traditional ECC.
- Radiation-Tolerant Memory Correction Using Retained Output State
A retained-output correction circuit lets redundant memory elements preserve the last correct value when radiation causes mismatched reads.
- Universal Error-Correction Circuit for Fault-Tolerant TMR Decoding
Logic-gate error correction replaces more complex TMR redundancy to handle module errors, lower frame error rates, and improve decoder reliability.
- Adder-Based Majority Voting for Redundant Logic Circuits
Shared adder and XOR logic replace separate majority voters in redundant IC circuits, cutting area and delay while flagging output errors.
- Power Gating Circuit With Sleep-Signal Acknowledge Feedback
Returning a buffered sleep signal as the acknowledge path cuts buffer count and leakage in power gating circuits for mobile devices.
- Circuit Subset Triplication for Automated Partial TMR
Automated ranking and selection of circuit subsets enables partial TMR that preserves memory states and improves fault recovery.
- Majority Determination Circuit Without Dummy Transistors
Two odd-bit determination units replace dummy transistors to improve even-bit majority decisions under noise and impedance mismatch.