FinFET Logic Circuits Using Dual-Gate Inputs for Area and Power Reduction
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Solution Overview
Problem
Conventional digital circuit designs face challenges in achieving low power and area efficiency, particularly with the scaling of transistors, as pass transistor logic suffers from voltage drops and increased transistor count, while FinFETs offer versatility but are underutilized beyond simple logic gates.
Innovation Solution
Implementing FinFET-based circuits using both gates as inputs, adopting an OR-AND logic expression and replacing NMOS and PMOS transistors with N-FinFETs and P-FinFETs, respectively, to design majority gates and 2-1 MUXs, resulting in reduced transistor count and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pass transistor logic is used to reduce transistor count, then area is reduced, but voltage drop occurs and full voltage swing cannot be achieved
Solution Approach 1:
The patent changes the transistor structure from planar to FinFET, utilizing the three-dimensional channel to improve carrier control and reduce threshold voltage effects. This structural parameter change enables the transistor to maintain full voltage swing while using fewer transistors, resolving the contradiction between area reduction and voltage swing reliability.
Solution Approach 2:
The FinFET transistor is segmented into multiple gates (front gate and back gate) that can be independently controlled. This segmentation allows for enhanced control over the channel, enabling better voltage swing performance while maintaining area efficiency through the vertical channel structure.
2Power
If FinFET back gate is used to enhance current drive, then transistor performance is improved, but device complexity increases
Solution Approach 1:
The back gate is designed to serve multiple functions: enhancing current drive when the front gate is active, and adjusting threshold voltage to reduce leakage when the front gate is inactive. This multi-functionality allows a single additional gate to provide both performance enhancement and power management, offsetting the increased device complexity with functional versatility.
Solution Approach 2:
The back gate voltage is dynamically adjusted based on the operational state of the transistor. When the front gate is ON, the back gate is biased to enhance current drive; when the front gate is OFF, the back gate is biased to increase threshold voltage and reduce leakage. This dynamic control optimizes performance while managing the complexity of dual-gate control.
3Area of stationary object
If FinFET is used to reduce transistor count for logic functions, then area is reduced, but circuit speed may slow down
Solution Approach 1:
The patent utilizes the vertical FinFET structure with its superior electrostatic control to achieve higher drive current density per transistor. This parameter change in transistor architecture compensates for the reduced transistor count by providing stronger individual transistor performance, thereby maintaining circuit speed while reducing area.
Solution Approach 2:
The back gate is pre-biased to optimize the threshold voltage and current drive characteristics before the front gate switches. This preliminary action ensures that when the transistor is activated, it operates at optimal performance levels, maintaining fast switching speeds despite using fewer transistors.
Data Source
AI summary
A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.