Threshold Logic Latch Circuit for Low-Leakage High-Speed CMOS
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Solution Overview
Problem
There is a need for a threshold logic gate with low leakage power and high performance characteristics, as existing solutions fail to efficiently implement digital logic functions while being robust to process variations.
Innovation Solution
The development of a Threshold Logic Latch (TLL) that operates in a current-mode threshold logic cell, comprising an input gate network, a threshold gate network, and a differential network, allowing for synchronous or asynchronous operation and compatibility with CMOS technology, with robustness to process variations through isolated control inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a threshold logic gate is designed for high performance, then speed and efficiency are improved, but leakage power increases
Solution Approach 1:
The threshold logic gate operates in periodic cycles between reset state and evaluation state. During the reset state, the output is forced to a known logic level and during the evaluation state, the actual computation occurs. This periodic operation allows the gate to maintain high performance during evaluation while controlling leakage power through the structured timing and state transitions.
Solution Approach 2:
The invention uses dynamic operation modes where the threshold logic gate can switch between different states (reset and evaluation) and supports both synchronous and asynchronous operation. The dynamic nature allows the gate to adapt its operation to minimize leakage while maintaining high performance when needed, particularly through the ability to enter low-power states between computations.
2Reliability
If a threshold logic gate is designed to be robust to process variations, then reliability is improved, but device complexity increases
Solution Approach 1:
The differential network structure creates symmetric pull-up and pull-down paths that are equipotential in design. This symmetry ensures that process variations affecting one path are compensated by the other, maintaining reliable operation. The differential configuration inherently rejects common-mode variations while preserving the logic function.
Solution Approach 2:
The invention employs parameter tuning through the threshold network where weighted sums of inputs are compared against a threshold value. By adjusting the threshold parameter and weights, the gate achieves robustness to process variations while maintaining the desired logic function. This parameter-based approach allows optimization without increasing structural complexity.
Data Source
AI summary
Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.