Flip-Flop Majority Voting Circuit for Faster Failure Detection
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Solution Overview
Problem
The existing failure detection methods for flip-flop circuits in semiconductor devices are time-consuming, requiring multiple tests to verify the operation of three flip-flop circuits and a majority logic circuit, especially when detecting failures caused by alpha rays, which can invert latch data and lead to malfunction.
Innovation Solution
A semiconductor device incorporating a majority logic circuit and a minority value determination circuit that outputs a first and second output value based on the majority and minority of output values from multiple flip-flop circuits, allowing for the detection of failures by comparing these values, thereby reducing the number of test combinations needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test combinations are used to verify the operation of three flip-flop circuits and a majority logic circuit, then the reliability of failure detection is improved, but the test time becomes excessively long
Solution Approach 1:
The patent segments the failure detection function into two independent circuits: a majority logic circuit that outputs the most frequent value among three flip-flops, and a minority value determination circuit that outputs the least frequent value. This segmentation allows each circuit to be tested independently with simpler test patterns, reducing the total number of test combinations required while maintaining comprehensive coverage of all failure modes.
Solution Approach 2:
The patent introduces an intermediary test mechanism where the minority value determination circuit acts as a mediator to detect failures in the majority logic circuit. By comparing the minority value with expected results, the system can identify failures without requiring exhaustive testing of all possible flip-flop combinations, thus reducing test time while preserving detection reliability.
2Reliability
If three flip-flop circuits are used for alpha-ray resistance, then the resistance to alpha-ray-induced malfunctions is improved, but the complexity of the circuit increases
Solution Approach 1:
The patent divides the alpha-ray resistant data hold circuit into three separate flip-flop circuits, each processing the same input data independently. This segmentation allows the system to tolerate alpha-ray-induced errors in individual flip-flops while maintaining overall correctness through majority voting, achieving high reliability without requiring a completely different circuit architecture.
Solution Approach 2:
The patent makes each flip-flop circuit universal by having all three circuits perform the same function of holding input data with their respective clock signals. This multi-functionality approach allows the system to achieve alpha-ray resistance through redundancy of identical functional units, rather than requiring specialized different circuits, thus managing complexity while improving reliability.
3Reliability
If separate clock signals are supplied to three flip-flop circuits, then the resistance to noise-induced malfunctions is improved, but the device complexity increases
Solution Approach 1:
The patent segments the clock signal distribution by providing separate clock signals (CLK1, CLK2, CLK3) to each of the three flip-flop circuits. This segmentation isolates the timing control of each flip-flop, preventing noise on one clock line from affecting the others, thereby improving noise resistance while keeping each clock path simple and independent.
Solution Approach 2:
The patent applies local quality by giving each flip-flop circuit its own dedicated clock signal with potentially different characteristics optimized for that specific circuit's location and timing requirements. This localized approach allows each flip-flop to operate optimally with its own clock parameters, improving overall system noise resistance without requiring a complex centralized clock distribution system.
Data Source
AI summary
A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.