Majority Determination Circuit Without Dummy Transistors
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Solution Overview
Problem
Conventional majority determination circuits in semiconductor devices face errors due to noise and impedance mismatch, particularly when determining the majority of bits, as they rely on dummy transistors which can introduce distortion.
Innovation Solution
A majority determination circuit that eliminates the need for dummy transistors by using multiple determination units to compare bits in odd-bit and even-bit data, ensuring accurate majority determination through result combination, thereby reducing errors caused by noise and impedance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy transistors are used in the majority determination circuit, then the circuit can determine majority in even-bit data, but errors occur due to noise and impedance mismatch
Solution Approach 1:
The patent divides even-bit data into two separate odd-bit data groups (first odd-bit data and second odd-bit data). Each group is processed by a separate determination unit that compares high-level and low-level bits independently. This segmentation eliminates the need for dummy transistors and their associated impedance mismatch problems, while maintaining the ability to determine majority in the original even-bit data through result combination.
2Productivity
If conventional majority determination circuit is used, then data processing speed can be increased through DBI, but errors are introduced by dummy transistors
Solution Approach 1:
By segmenting even-bit data into two odd-bit groups and processing them separately without dummy transistors, the patent eliminates error sources while maintaining DBI functionality for high-speed data processing.
Solution Approach 2:
The patent creates a copy of the determination logic for the second odd-bit data group, mirroring the first determination unit. This copying approach allows parallel processing of both data groups without requiring dummy transistors, thus maintaining high processing speed while improving reliability through redundant verification.
Data Source
AI summary
A majority determination circuit includes a first determination unit suitable for determining a first majority between bits of a first logic value and a second logic value in a first odd-bit data, wherein the first odd-bit data is an even-bit data with absence of first bit, a second determination unit suitable for determining a second majority between bits of the first logic value and the second logic value in a second odd-bit data, wherein the second odd-bit data is the even-bit data with absence of second bit, and a result combination unit suitable for determining a third majority between bits of the first logic value and the second logic value in an even-bit data based on the first majority and the second majority.