Universal Error-Correction Circuit for Fault-Tolerant TMR Decoding
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Solution Overview
Problem
Current triple modular redundancy (TMR) systems, while providing fault-tolerant capabilities, suffer from increased hardware complexity and limited error-correction capabilities, particularly when errors occur within the redundancy module, failing to meet stringent precision requirements in fields like aerospace and medicine.
Innovation Solution
A universal error-correction circuit with a fault-tolerant nature, implemented using logic gates, which includes an error-correction unit that processes digital input signals to produce output signals, and a decoder comprising a variable node module, interleaver, check node module, and de-interleaver, enhancing fault-tolerance and error-correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy (TMR) is used to provide fault-tolerant capabilities, then system reliability is improved, but hardware complexity increases significantly
Solution Approach 1:
The patent combines multiple TMR modules into a unified error correction circuit that shares common resources and logic. The encoder and decoder circuits are merged to work cooperatively, reducing redundant hardware while maintaining the fault-tolerant capability of correcting up to two errors simultaneously.
Solution Approach 2:
The error correction circuit is designed as a universal solution that can handle multiple error types (single errors, double errors, and frame errors) through a single integrated structure. The same circuit architecture serves both encoding and decoding functions, making the system multi-functional without requiring separate dedicated circuits for each error scenario.
2Reliability
If traditional TMR systems are used, then fault-tolerant capability is provided, but error-correction capability is limited when errors occur within the redundancy module
Solution Approach 1:
The patent implements feedback mechanisms where the encoder circuit generates syndrome information that is fed back to the decoder circuit for error detection and correction. The decoder uses this feedback to identify and correct errors in the input signals, enabling the system to handle errors within the redundancy module that traditional TMR cannot correct.
Solution Approach 2:
The encoder circuit performs preliminary error detection and preparation of syndrome information before the actual decoding process. By pre-processing the input signals and generating correction data in advance, the system is better prepared to handle errors that occur during transmission or within the redundancy module, improving overall error-correction capability.
3Reliability
If triple modular redundancy is implemented, then system fault-tolerance is enhanced, but the circuit complexity and resource consumption increase
Solution Approach 1:
The patent segments the error correction functionality into distinct encoder and decoder modules with clear interfaces. Each module handles specific aspects of error correction independently, allowing for modular design that reduces overall circuit complexity while maintaining comprehensive fault-tolerance capabilities through coordinated operation of the segments.
Data Source
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AI summary
The present invention provides a universal error-correction circuit with fault-tolerant nature, and a decoder and a triple modular redundancy circuit that apply it, where the universal error-correction circuit with fault-tolerant nature includes: an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 ..., I2k-1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1..., Ok-2, and Ok-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to: when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok-1 = I2k-1 if Ok-2=I2k-1, and Ok-1 = I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate. There may be a plurality of specific implementation manners, as long as input and output meet the uniquely certain logical relationship of the present invention. Therefore, the error-correction circuit with fault-tolerant nature provided by the present invention is provided with general commonality.