Adder-Based Majority Voting for Redundant Logic Circuits
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Solution Overview
Problem
Integrated circuits face increased cost and delay due to the requirement of multiple copies of designs and majority voting circuitry for multi-mode redundancy to detect and correct single event upsets, which consumes more circuit area.
Innovation Solution
Implementing a programmable integrated circuit with first and second circuits where the second circuit computes a sum of signals and produces a majority signal based on a majority vote function, utilizing shared sub-circuits and adders to reduce resource requirements, and incorporating a logic exclusive OR gate to indicate errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple copies of design and majority voting circuitry are implemented for multi-mode redundancy, then error detection and correction capability is improved, but circuit area and implementation cost increase
Solution Approach 1:
The patent combines multiple design copies and majority voting circuitry into a single integrated circuit structure where redundant logic elements share common interconnect resources. Multiple logic elements are coupled to a single adder circuit that performs both arithmetic addition and majority vote functions, thereby reducing the total circuit area while maintaining error detection and correction capabilities.
Solution Approach 2:
The adder circuit is designed to serve dual purposes: performing arithmetic addition operations for normal computation and simultaneously functioning as a majority vote circuit for error detection and correction. This multi-functionality eliminates the need for separate dedicated majority voting circuitry, reducing overall circuit area and resource requirements.
2Reliability
If multiple copies of design and majority voting circuitry are implemented for multi-mode redundancy, then error detection and correction capability is improved, but implementation delay increases
Solution Approach 1:
By merging the arithmetic logic unit and majority vote circuitry into a single integrated structure, the patent eliminates the need for sequential processing through separate circuit stages. The adder circuit simultaneously computes both the sum and majority vote results from multiple logic element outputs in parallel, thereby reducing the overall implementation delay while maintaining robust error detection and correction functionality.
3Reliability
If multiple copies of design are implemented for multi-mode redundancy, then error detection and correction capability is improved, but resource requirements increase
Solution Approach 1:
The patent merges multiple logic element outputs into a shared adder circuit that consolidates computational resources. Instead of requiring separate processing paths for each redundant design copy, the adder circuit efficiently combines inputs from multiple logic elements performing the same function, thereby reducing interconnect resources and overall device complexity while maintaining multi-mode redundancy capabilities.
Solution Approach 2:
The adder circuit is designed as a universal resource that performs both arithmetic addition and majority vote operations. This single circuit structure replaces what would traditionally require separate dedicated circuits for each function, significantly reducing the overall resource requirements including logic elements, interconnects, and routing resources needed to implement error detection and correction.
Data Source
AI summary
Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.