One-Shot Flash NCL Gate Reset for Faster Go-to-Data Cycles

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Solution Overview

Problem

Flash null convention logic (NCL) circuits face challenges in generating a correct and timely flash signal within stringent delay specifications, leading to delays in the 'Go to Data' cycle, which affects the performance of NCL logic gates.

Innovation Solution

Incorporating a one-shot circuit with the NCL gate to generate timing signals for resetting the circuit, eliminating delays and enhancing performance by providing a direct mechanism for resetting instead of waiting for nulls to propagate through stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional NCL gate waits for nulls to propagate through stages for resetting, then the circuit structure remains simple, but the delay increases and performance deteriorates

Engineering Contradiction:
Improvereset speedVSAvoidcircuit complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The one-shot circuit is pre-configured with the flash signal and output line connections before operation. When the flash signal transitions, the one-shot circuit immediately generates the reset pulse without waiting for null propagation, performing the reset action in advance of the conventional method and eliminating the delay.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The one-shot circuit acts as an intermediary component between the flash signal and the reset mechanism. It receives the flash signal and output line states, processes them through its internal timing circuitry, and generates the appropriate reset pulse, mediating the reset process to achieve faster performance while maintaining manageable circuit complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the flash signal generation follows conventional timing methods, then the circuit design is straightforward, but the delay specification cannot be met

Engineering Contradiction:
Improvetiming precisionVSAvoidcircuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The one-shot circuit implements periodic action by generating a precisely timed reset pulse of fixed duration in response to the flash signal transition. This periodic pulse generation mechanism ensures that the reset occurs at the exact moment needed to meet delay specifications, providing manufacturing-level timing precision that conventional continuous timing methods cannot achieve.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The one-shot circuit changes its operational parameters dynamically based on the flash signal state and output line conditions. When triggered, it transitions from a stable state to an active pulse-generating state, then returns to stable, changing timing parameters to achieve the required precision while keeping the overall circuit design relatively simple.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If null propagation is used for resetting, then the control mechanism is simple, but the 'Go to Data' cycle is delayed

Engineering Contradiction:
Improvecycle throughputVSAvoidreset delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The one-shot circuit extracts the essential timing function from the null propagation mechanism. Instead of relying on the slow propagation of null signals through multiple stages, the one-shot circuit directly generates the reset pulse based on the flash signal, taking out the timing control function and separating it from the data propagation path, thereby eliminating the reset delay and improving cycle throughput.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The one-shot circuit is self-triggered by the flash signal and self-terminates the reset pulse based on its internal timing mechanism. It does not require external control signals or complex coordination with other circuit stages, serving itself to generate the appropriate reset timing autonomously, which improves productivity without adding significant control complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8981812B2Self-ready flash null convention logic
Publication Date: 2015.03.17 MIPS HLDG INC
  • US8981812B2 patent drawing
  • US8981812B2 patent drawing
  • US8981812B2 patent drawing

AI summary

A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state.