Self-Correcting Voting Latches for SEU-Resistant TMR Circuits
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Solution Overview
Problem
Triple modular redundancy (TMR) circuits in programmable integrated circuits face errors due to single event upsets (SEUs) caused by atmospheric radiation, which existing voting circuits fail to mitigate efficiently, leading to errors in configuration and logic upsets.
Innovation Solution
A voting circuit design using pull-up and pull-down circuits connected to bi-stable circuits, which self-corrects errors by pulling the output node to a positive supply voltage or ground based on complementary output signals from multiple bi-stable circuits, reducing the transistor count from 18 to 4 and enabling self-correction of one or all latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional voting circuits are used in TMR circuits, then reliability against SEUs is improved, but device complexity and transistor count increase
Solution Approach 1:
The patent combines the voting circuit functionality with the latch circuits by sharing transistors between the voting logic and latch structures. The pull-up and pull-down circuits are merged with the latch transistors, allowing the same hardware to perform both voting and state storage functions, thereby reducing overall transistor count from 18 to 4 per voting-latch unit.
Solution Approach 2:
The voting circuit transistors serve multiple functions: they act as both voting logic elements (comparing three inputs) and as latch storage elements. The pull-up and pull-down circuits simultaneously perform voting decision and state memory functions, eliminating the need for separate dedicated voting and storage components.
2Reliability
If redundant bi-stable circuits are added for TMR, then immunity to SEUs is improved, but the circuit size and power consumption increase
Solution Approach 1:
The patent merges the voting circuit with the latch circuits, sharing transistors between the three redundant paths. Instead of having completely separate voting logic and latch structures, the same transistors perform both functions, reducing the total quantity of circuit elements while maintaining TMR redundancy.
Solution Approach 2:
Each transistor in the voting circuit serves multiple purposes: it participates in the voting decision process and simultaneously functions as a storage element for the redundant latch. This multi-functionality reduces the overall circuit size compared to traditional implementations with separate dedicated components.
Data Source
AI summary
The disclosed voting circuit includes a pull-up circuit connected to an output node and to a positive supply voltage. A pull-down circuit is connected to the output node and to ground, and the output node is coupled to receive true output of a first bi-stable circuit. The pull-up circuit pulls the output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and the pull-down circuit pulls the output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state.