NCL Mesh Clock Circuit for Low-Skew Chip Synchronization
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Solution Overview
Problem
The complexity of clock signal distribution in highly advanced integrated circuits leads to challenges in minimizing signal skew, which increases power dissipation and reduces the maximum clock rate due to the need for extensive wiring and additional circuitry like retimers and buffers.
Innovation Solution
A mesh circuit comprising null convention logic (NCL) gates organized into rings, where each ring operates synchronously with others, sharing at least one NCL gate to coordinate synchronization signals and reduce signal skew, thereby simplifying clock distribution and reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a metal distribution grid with retimers, buffers, and amplifiers is used to deliver clock signal, then clock signal skew is minimized, but power dissipation increases and maximum clock rate decreases
Solution Approach 1:
The patent extracts and eliminates the need for retimers, buffers, and amplifiers from the clock distribution system by using a synchronous event-driven architecture where the mesh network inherently maintains signal integrity through its topology and NCL gate characteristics, removing these power-consuming components entirely
Solution Approach 2:
The system uses periodic synchronization tokens circulating through the mesh network to maintain clock coherence without requiring continuous power-intensive buffering and amplification, achieving periodic resynchronization that reduces overall power consumption
2Loss of time
If retimers, buffers, and amplifiers are added to clock distribution lines, then propagation time is minimized, but power dissipation increases and maximum clock rate is reduced
Solution Approach 1:
The mesh network dynamically adapts signal propagation through its reconfigurable NCL gates that can adjust their behavior based on local conditions, allowing optimal signal timing without fixed buffering stages that consume continuous power
Solution Approach 2:
The NCL gates in the mesh network self-regulate signal propagation timing through their inherent null-convention logic operation, eliminating the need for external power-intensive buffering and amplification while maintaining synchronization
3Measurement precision
If extensive wiring and additional circuitry are used for clock distribution, then signal skew is controlled, but device complexity increases
Solution Approach 1:
The mesh network serves multiple functions simultaneously: it provides clock distribution, signal synchronization, and timing control through its unified NCL gate structure, eliminating the need for separate dedicated retimer, buffer, and amplifier circuits
Solution Approach 2:
The patent merges the clock distribution function with the data signal routing infrastructure by using the existing mesh network for both purposes, consolidating what would traditionally require separate dedicated clock trees into a unified structure
Data Source
AI summary
Systems and methods for clock generation and distribution are disclosed. Embodiments include arrangements of synchronization signals implemented using a mesh circuit. The mesh circuit is comprised of a plurality of null convention logic (NCL) gates organized into rings. Each ring shares at least one NCL gate with an adjacent ring. The rings are configured in such a way that each ring in the mesh operates synchronously with the other rings in the mesh.