3D Gate-All-Around Transistor Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties.
Innovation Solution
A semiconductor device design featuring a three-dimensional field effect transistor with a gate electrode that three-dimensionally surrounds the channel pattern, incorporating a high-k dielectric layer and a dielectric layer between the gate contact and electrode to manage voltage and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device density and integration are improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple channel patterns are stacked in the vertical direction (third direction) to increase effective channel width without increasing lateral footprint. This dimensional transition allows continued scaling while maintaining operational properties by providing sufficient channel width for proper transistor operation.
Solution Approach 2:
The patent implements nested structures where gate electrodes surround channel patterns in a gate-all-around configuration. The gate electrode is divided into multiple portions that wrap around each channel pattern from different directions, creating a nested arrangement that maximizes gate control over the channel while minimizing the lateral space required.
2Device complexity
If gate contacts are directly connected to gate electrodes without intermediate dielectric layers, then manufacturing complexity is reduced, but voltage management and reliability deteriorate
Solution Approach 1:
The patent introduces dielectric layers as intermediary elements between gate contacts and gate electrodes. These dielectric layers serve as insulating barriers that prevent direct electrical contact, enabling independent voltage control of different gate portions. The dielectric layers are integrated into the manufacturing process through conformal deposition steps that add minimal process complexity while providing essential voltage management functionality.
3Ease of manufacture
If conventional planar channel structures are used, then manufacturing is simpler, but effective channel width is insufficient for scaled devices
Solution Approach 1:
The patent stacks multiple channel patterns vertically in the third direction to increase effective channel width without increasing lateral dimensions. This vertical stacking approach maintains compatibility with conventional planar manufacturing processes while achieving the required channel width through the vertical dimension, thus resolving the contradiction between manufacturing simplicity and sufficient channel width.
Solution Approach 2:
The patent divides the channel structure into multiple discrete channel patterns that are stacked vertically. Each channel pattern can be independently formed and controlled, allowing the effective channel width to be increased by adding more stacked segments rather than requiring a single large lateral dimension that would complicate manufacturing.
4Ease of manufacture
If gate electrodes are positioned only above channel patterns, then manufacturing is easier, but gate control over channel is insufficient
Solution Approach 1:
The patent implements gate-all-around structures where gate electrodes are positioned to surround channel patterns from multiple directions. The gate electrode is segmented into multiple portions that wrap around the channel, providing comprehensive electrostatic control. This nested arrangement ensures that the gate potential is applied uniformly from all sides, significantly improving gate control compared to conventional top-only gate configurations.
Solution Approach 2:
The patent extends gate electrode positioning from a single planar dimension to three-dimensional space surrounding the channel. Gate portions are positioned above, below, and at the sides of channel patterns, utilizing the vertical and lateral dimensions to achieve complete gate wraparound. This multi-dimensional gate placement provides superior channel control while remaining compatible with advanced semiconductor manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical and reliability characteristics of semiconductor devices by reducing voltage applied to high-power transistors and preventing reliability issues.
Implementation Method 1
a first dielectric layer interposed between the first gate contact and the first gate electrode
Implementation Method 2
incorporating a high-k dielectric layer and a dielectric layer between the gate contact and electrode to manage voltage and improve reliability
Data Source
AI summary
A semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.