3D Channel Gate Structure With Variable Blocking Insulation
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density while maintaining improved electrical properties and reliability, particularly in three-dimensional channel structures.
Innovation Solution
The semiconductor device incorporates a substrate with an active pattern, multiple channel layers stacked perpendicular to the substrate, a gate structure crossing the active pattern, and source/drain patterns connected to the channel layers. The device also features blocking insulating layers with varying thicknesses and a metal-semiconductor compound layer to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional channel structures are used to increase integration density, then integration density is improved, but contact resistance and parasitic capacitance increase
Solution Approach 1:
The blocking insulating layer is designed with non-uniform thickness, being thicker at the lower region adjacent to the channel layer and thinner at the upper region. This local variation in thickness optimizes the balance between reducing parasitic capacitance (thinner upper region) and maintaining electrical isolation/reducing contact resistance (thicker lower region), thereby improving overall electrical properties while preserving the three-dimensional structure's integration density benefits.
Solution Approach 2:
The patent changes the thickness parameter of the blocking insulating layer to resolve the contradiction. By setting the lower region thickness to be greater than the upper region thickness, the design optimizes electrical properties without sacrificing the integration density achieved through three-dimensional channel structures.
2Ease of manufacture
If blocking insulating layers with uniform thickness are used, then manufacturing simplicity is maintained, but electrical properties deteriorate due to increased parasitic capacitance
Solution Approach 1:
The blocking insulating layer employs local quality variation with different thicknesses in different regions. The lower region has greater thickness to reduce parasitic capacitance, while the upper region has lesser thickness. This non-uniform design improves electrical properties while remaining manufacturable through standard deposition processes.
3Reliability
If thicker blocking insulating layers are used throughout, then parasitic capacitance is reduced, but contact resistance increases and manufacturing complexity increases
Solution Approach 1:
Rather than uniformly increasing blocking insulating layer thickness, the patent applies local quality by making the lower region thicker than the upper region. This targeted approach reduces parasitic capacitance where it matters most (near the channel layer) while avoiding the drawbacks of uniform thickness increase, thereby reducing contact resistance and maintaining manufacturing simplicity.
Solution Approach 2:
The patent applies partial action by increasing the blocking insulating layer thickness only in the lower region where it is most needed for capacitance reduction, rather than excessively increasing thickness throughout the entire structure. This optimized approach achieves the desired electrical performance without unnecessary complexity.
Data Source
AI summary
A semiconductor device includes a substrate; an active pattern extending on the substrate in a first direction; a plurality of channel layers on the active pattern; a gate structure surrounding the plurality of channel layers, and extending in a second direction that intersects the first direction; blocking insulating layers on both side surfaces of the gate structure, respectively, each of the blocking insulating layers having an upper region having a first thickness and a lower region having a second thickness smaller than the first thickness; source/drain patterns on portions of the active pattern on both sides of the gate structure, the source/drain patterns defining trenches therein; contact structures on the source/drain patterns and filling the trenches; and a metal-semiconductor compound layer between the source/drain patterns and the contact structures.