3D High-Voltage Gate Dielectric Liners for Isolation Reliability
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Solution Overview
Problem
Conventional fabrication approaches struggle to support high voltage transistors on aggressively scaled three-dimensional device architectures due to reduced isolation thickness between gate and source/drain contacts, leading to premature device failure and reliability issues.
Innovation Solution
The implementation of an inside spacer dielectric liner process, which involves forming multiple dielectric layers to increase sidewall spacing between the gate material and adjacent source and/or drain contacts, using a replacement metal gate process flow to provide additional dielectric margin for scaled high voltage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication approaches are used for scaled transistors, then device density is improved, but isolation thickness between gate and contacts is reduced leading to premature failure
Solution Approach 1:
The gate dielectric structure is segmented into multiple distinct layers: a first dielectric layer formed directly on the semiconductor body, and a second dielectric layer formed over the first dielectric layer. This segmentation allows each layer to be optimized independently for different functional requirements, enabling both high device density and sufficient isolation thickness for reliability.
Solution Approach 2:
The patent introduces a vertical dimension to the dielectric structure by forming a second dielectric layer over the first dielectric layer. This vertical stacking approach increases the total isolation thickness between the gate and adjacent contacts without increasing the lateral footprint, thereby maintaining high device density while improving reliability through enhanced electrical isolation.
2Reliability
If multiple dielectric layers are formed to increase isolation thickness, then reliability is improved, but device complexity increases
Solution Approach 1:
The first dielectric layer is formed preliminarily on the semiconductor body before the gate structure is fully defined. This preliminary action establishes a foundation for subsequent processing steps and enables the second dielectric layer to be formed with proper alignment and spacing, reducing the complexity of later fabrication steps.
Solution Approach 2:
The patent employs parameter changes by forming the first dielectric layer with specific material properties and thickness characteristics, then forming the second dielectric layer with different material properties and thickness. This differentiation allows optimization of electrical isolation while managing fabrication complexity through controlled parameter variations.
Data Source
AI summary
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.