Solid-State Devices TRIZ Cases

A vertically stacked micro LED epitaxial structure combines multiple wavelengths in one pixel to avoid complex transfer steps and enable 5000 ppi displays.

Vertical cylindrical emitters and alignment electrodes direct light forward, boosting luminance and reducing color mixing in displays.

Triple-exposure hexagonal patterning turns etch load effects into circular connecting pads, improving pad uniformity and preventing capacitor leakage.

A pixel-integrated MIM capacitor boosts capacitance and sensitivity without enlarging pixel size, while the metal light shield protects the reading circuit.

A backside groove vents trapped air during semiconductor bonding, preventing bubbles and improving positional accuracy on the substrate.

Direct silver cathode contact with a phosphine oxide electron transport layer improves charge balance, lowers power use, and extends OLED life.

A P-type region separates the N-type diffusion layer from the backside Si interface to preserve charge pinning and suppress white spots.

Direct oxide contact with an LTPS active pattern boosts TFT electron mobility and electrical characteristics for higher-quality displays.

Top- and bottom-emitting micro LEDs on one transmissive substrate cut panel thickness and weight while shielding stray light for clearer images.

A crystalline-etched horizontal and vertical light shield blocks stray light from the charge-holding section to suppress noise in backside imaging sensors.

Low-temperature regrown doped source-drain regions cut TFT external resistance and preserve channel mobility during device-level integration.

A key pattern above a dummy pillar improves 3D memory stack alignment, reducing process defects while stabilizing cell connections.

Non-Gaussian laser pulses focused inside the wafer create internal breakage for precise dicing while limiting melting and device damage.

A variable-thickness isolation dielectric and etched-back conductive trench pattern improve pixel isolation, dark current suppression, and yield.

Smaller inter-board LED gaps and light-shielding parts cut visible seams while improving bonding yield in large spliced micro LED panels.

Through-holes in the insulating layer localize ETL and injection layers to improve OLED film uniformity, prevent leakage, and raise yield.

Taller light shields around larger on-chip lenses curb optical color mixing while maintaining sensitivity and improving image quality.

Surface plasmon polaritons and split energy bands enable compact photodetectors to sense long wavelengths with higher quantum efficiency.

Placing the electrode layer over the spacer unit increases line spacing, cuts capacitance, and lowers LCD array substrate cost.

A SiCN dielectric and etch-stop layer block re-sputtered bottom-electrode metal, preventing MTJ sidewall shorts in MRAM.

Independent control of pixel-group exposure and readout timing improves image quality and dynamic range under varied lighting conditions.

An interdigitated GaN transistor-Schottky layout lowers reverse conduction voltage while preserving forward conduction and simplifying integration.

A peripheral optical filter blocks visible-light leakage into the infrared conversion unit, improving SNR, resolution, and ranging accuracy.

Varying stair depths in 3D memory arrays improve conductor-tier access and structural integrity without uniformly increasing stair-step complexity.

Electrodes formed partly on insulating banks act as reflective partitions, simplifying display fabrication while increasing pixel density and light output.

Multiple dielectric liner layers increase gate-to-contact spacing in scaled 3D transistors, improving breakdown voltage and high-voltage reliability.

Heteroepitaxial compound semiconductor layers on silicon expand photodetector wavelength range and sensitivity while remaining CMOS compatible.

A deformable conductive layer shorts pixel and common or ground electrodes at shutdown to release residual charge and reduce LCD image retention.

IGZO channel transistors cut DRAM sub-threshold leakage, extending refresh intervals while supporting dense, low-temperature memory arrays.

Molded package body fillets around spaced semiconductor chips improve LED light outcoupling while keeping the package compact and accessible.

Sorting microLED tiles by size, edge straightness, and squareness enables tighter registration pitch and more uniform display assembly.

A segmented-gate global shutter improves charge holding, lowers off-state leakage and power use, and supports short-duration 3D imaging.

Heat dissipation vias in the support substrate create a direct thermal path for stacked RAM in a 3D SiP, improving cooling without TSVs.

Integrated package antennas replace lossy high-frequency wiring, enabling flexible chip-to-chip LO signal transfer and radar position sensing.

A self-aligned metal and trench isolation grid avoids dry-etch silicon damage and improves optical isolation in BSI image sensors.

Groove-protrusion pad joining removes visible seams in tiled displays while maintaining electrical connection through anisotropic conductive films.

Sequential metal deposition and oxidation form an MRAM MTJ cap layer that improves flatness, reduces stress, and limits over-oxidation.

A dielectric structure over DTI fixes spacing to floating diffusion nodes, cutting dark current and white pixels in small-pixel image sensors.

Preformed adhesive recesses and a shaping support enable batch bending of microelectronic components with accurate curvature and optical integrity.

Paired embedded gate units modulate deep substrate potential to prevent charge return to the photodiode during CMOS readout.

Asymmetric color filter protrusions and a light-shield pattern balance sensitivity near autofocus pixels and improve image quality.

A three-layer epitaxial base balances high breakdown voltage and shallow snapback in vertical BJT ESD protection while reducing latch-up risk.

Epitaxial overgrowth forms multi-color micro-LEDs without mesa etching, cutting sidewall defects and improving light emission efficiency.

Matched fin-transistor I/O levels let stacked DRAM and logic chips couple directly, cutting memory-wall latency, power, and interface complexity.

Multiple silicon dice split a SPAD line array, while lens overlap steers light away from die gaps for accurate depth sensing and better low-light imaging.

Light-spreading lenses over SPAD arrays lower photon density to prevent saturation while improving low-light 3D time-of-flight imaging.

Top selective gate cuts placed between channel rows shrink memory finger area by 5-10% while easing gate replacement in 3D memory fabrication.

Boundary-height structures outside the imaging region keep planarization uniform, stabilizing on-chip lens focusing and sensor yield.

Combining large- and small-area SiPM cells extends LiDAR photon detection range while preserving low-light sensitivity and limiting saturation.

Multiple shift register groups inside the display area shorten scan-line RC loading, improving charging time and brightness uniformity.

A ferroelectric layer stabilizes oxygen ions within memory cell electrodes, preventing drift back into the source material and ensuring stable data retention.

A pixel isolating film covers pixel electrode ends to provide electrical insulation and reduce charge leakage.

Integrating photodetectors into OLED display pixels enables optical fingerprint sensing without separate sensor modules.

Segmented pixel electrodes with specific stem arrangements compensate for substrate misalignment caused by curvature, maintaining luminance.

A liquid crystal display panel uses a three-dimensional protrusion pattern to define pixel boundaries and maintain aperture ratio.

Nano-scale grooves in the planarization layer guide sub-pixel electrode placement, preventing Mura abnormality and ensuring reliable 3D display operation.

Segmented links and selective plug contact enable multi-bit storage without narrowing line widths, overcoming semiconductor integration density limits.

A storage device design shares a floating potential film among memory cells to reduce size and increase capacity.

Multi-layered hole transport structure with cyano group doping increases free hole concentration in organic light-emitting diodes.

Dedicated clock buses route signals between transceivers to maintain signal integrity at high data rates exceeding 1 Gbps.

Black matrices on touch control electrodes shield units and reduce ambient light reflections, improving light extraction efficiency in flexible displays.

An extended bottom plate in a trench increases effective contact area, boosting capacitance without expanding the horizontal footprint.

A display substrate design uses a light shielding layer to electrically connect signal lines and terminals within grooves.

Surface light scattering sections control wavelength conversion to maintain chromaticity consistency during mass production.

Blockers on metallic wires shield conductive traces from falling particles, preventing wire flaws and displacement that degrade display quality.

An optical mask uses a photothermal conversion layer with alternating high and low light absorptivity regions to manage thermal energy distribution.

A distributed electrostatic discharge protection circuit uses a secondary network to shunt current away from sensitive integrated circuit components.

A Hall-effect working electrode pixel detects magnetic fields to transform handwritten marks into digital images.

Incorporating a dipole material in the OLED intermediate layer reduces interfacial resistance, improving luminous efficiency and extending service life.

Segmenting the p+ region into a lattice structure increases current path area, reducing on-resistance while maintaining breakdown voltage.

A metal grid in the buffer layer absorbs high angle light between photodiodes, reducing optical crosstalk for HDR imaging.

A semi-finished electronic device design integrates a lid and substrate to form a testing cavity for the sensing module.

Aligning TFT channel lengths with low-expansion substrate directions resolves the trade-off between display flexibility and position accuracy during production.

Merges the first drain electrode with the anode electrode to form a protective capacitor structure.

Lowering the third conductive layer surface reduces inter-level dielectric thickness, simplifying etching and cutting manufacturing costs.

An Sb2Te3:N barrier layer stops Ge atom diffusion, increasing rewriting cycles without adding manufacturing complexity.

Van der Waals buffer layers enable selective lift-off of patterned thin films via stressor-induced mechanical separation, resolving integration complexity.

A semiconductor memory device uses a vertical bipolar transistor structure to reduce the length of the selective element in the bit line direction.

Splitting the long select gate creates a gap for precise drain placement, reducing manufacturing complexity.

High-concentration perfluoro polymer formulation creates uniform 100 μm thick encapsulation layers that resist thermal stress and maintain LED brightness.

A conductive portion discharges electric charges to the semiconductor substrate during high aspect ratio etching.

A nanopatterned first electrode reflects light to an active layer, increasing absorbance without thickening the organic photoelectronic device.

A vertical gate memory device uses a P-type semiconductor pattern to contact channel layer sidewalls for direct hole injection during erase operations.

Warmer white balance reduces blue emission in RGBW OLED displays, lowering drive current and operating temperature for phosphorescent emitters.

Applying asymmetric bias voltages reduces power consumption and signal peaking in ferroelectric memory cells while maintaining switching reliability.

A quantum dot light detecting system uses a charge carrier extractor to convert optical energy into electrical signals.

Gate structure extensions partially enclose source and drain regions in the substrate, preventing leakage into photodiodes and reducing dark currents.

A pixel arrangement uses auxiliary metal lines on a ceramic substrate to route electrical signals between adjacent optical cells.

A solid-state imaging device uses an island-shaped semiconductor structure with a transparent conductive pixel selection line to expand the light-receiving section area.

Low-resistance tungsten bit lines use CMP and doping to lower sheet resistance, overcoming thin resist etch margin limits in sub-80 nm devices.

Diagonal gate line portions enable single-edge driver placement, minimizing border size while maintaining display layout flexibility.

Transparent conductive oxide layers block external reflection without absorbing emitted light, solving contrast and thickness trade-offs.

Extended isoindigo polymers with branched alkyl side chains enable solution processing of organic thin film transistors.

Thermally activated delayed fluorescent materials utilize reverse intersystem crossing to transform triplet excitons into singlet states.

An organic radiation detector integrates a photoelectric conversion layer with an electroluminescent light-emitting part to generate visible signals from incident radiation.

An ytterbium intermediate layer contacts a sodium fluoride electron transport layer to increase electron current amount and extend service life.

A dynamic-VT transistor adjusts its voltage threshold to balance switching speed and power consumption.

A metal-doped molybdenum oxide transparent electrode replaces conventional oxides in perovskite solar cells to boost light transmittance.

Deep trench isolation removes dark current parasitic signals while buried insulated electrodes maintain high infrared absorption efficiency.