Regrown Source-Drain TFT Structure for Low-Resistance Integration
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Solution Overview
Problem
Thin film transistors (TFTs) exhibit high on-state resistance, limiting the performance of integrated circuits, especially in portable electronic applications, due to the challenges of integrating transistor device levels at low temperatures without detrimental impact on previously fabricated transistors.
Innovation Solution
The use of regrown, impurity-doped source and drain materials with compositions distinct from the channel material, deposited at low temperatures (<450°C), to reduce parasitic external resistance and enhance channel mobility, while maintaining the integrity of existing transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin film transistors are fabricated with conventional source and drain materials, then device integration can proceed, but the on-state resistance remains high which limits circuit performance
Solution Approach 1:
The patent changes the material composition parameter of source and drain regions by incorporating group III elements (Ga, In) and group V elements (As, Sb, Bi) into the semiconductor layer, creating alloy compositions that fundamentally alter the electrical properties. This compositional parameter change enables simultaneous achievement of low on-state resistance and high channel mobility through optimized material chemistry rather than structural modification alone
Solution Approach 2:
The patent employs composite semiconductor materials formed by combining group IV elements (Si, Ge) with group III and group V elements to create complex alloy compositions in source and drain regions. These composite materials exhibit synergistic properties where the combination of elements produces superior electrical characteristics compared to conventional single-element or binary compounds, enabling both low resistance and high mobility
2Reliability
If high temperature processing is used to reduce source and drain resistance, then resistance decreases, but previously fabricated transistors on the same substrate are damaged
Solution Approach 1:
The patent changes the material composition to enable low-temperature processing by incorporating elements with lower melting points and more favorable phase stability at reduced temperatures. The group III-V alloy compositions allow for effective dopant activation and resistance reduction at temperatures below 450°C, avoiding the thermal damage to previously fabricated devices while still achieving the desired electrical properties
Solution Approach 2:
The patent introduces specially designed alloy compositions as intermediary materials between the conventional processing capabilities and the desired low-resistance state. These intermediate material compositions serve as a bridge, enabling gradual optimization of electrical properties through controlled composition adjustments rather than requiring extreme temperature processing that would damage existing devices
3Temperature
If thin film semiconductor materials are deposited at low temperatures for integration compatibility, then device level integration is achieved, but channel mobility remains limited
Solution Approach 1:
The patent changes the material composition parameter by incorporating group III and group V elements into the channel-forming semiconductor layer at low deposition temperatures. This compositional modification enables the material to maintain crystalline quality and high carrier mobility despite the low processing temperature, as the alloying elements facilitate better lattice formation and reduce scattering mechanisms that typically plague low-temperature deposited films
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in TFT structures with significantly lower external resistance and higher channel mobility, enabling more efficient integration of transistor levels in integrated circuits without compromising the performance of existing transistors.
Implementation Method 1
deposited at low temperatures (<450°C)
Data Source
AI summary
Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.