Low-Resistance Tungsten Bit Line Formation
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Solution Overview
Problem
In sub-80 nm semiconductor devices, the existing photolithography and Reactive Ion Etch (RIE) techniques using KrF light sources are inadequate for forming bit lines due to limitations in pattern formation and etch process margins, particularly with the ArF light source requiring thin resist with low etch selectivity, which complicates the etching process.
Innovation Solution
A method involving the formation of bit lines using a low-resistance tungsten layer through a RIE process, including forming contact holes, depositing a barrier metal layer, and employing Chemical-Mechanical Polishing (CMP) to reduce surface roughness, while using B2H6 or SiH4 doping to enhance tungsten grain size and reduce sheet resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ArF light source is used for sub-80 nm devices, then resolution is improved, but etch process margin is reduced due to low etch selectivity of thin resist
Solution Approach 1:
A mandrel structure is introduced as an intermediary element between the photoresist pattern and the final bit line pattern. The mandrel serves as a sacrificial template that enables pattern transfer with improved etch margins, allowing the use of thinner resist while maintaining sufficient etch selectivity and process window for sub-80 nm fabrication
2Device complexity
If conventional RIE method is used for bit line formation, then process simplicity is maintained, but sheet resistance is high
Solution Approach 1:
The material parameter of the bit line is changed from conventional polysilicon or tungsten silicide to low-resistance tungsten. This parameter change reduces sheet resistance by approximately 10 times while maintaining compatibility with the RIE fabrication process, thereby improving device performance without significantly increasing process complexity
3Adaptability or versatility
If polysilicon or tungsten silicide is used for bit line, then process compatibility is maintained, but device speed is limited due to high resistivity
Solution Approach 1:
The electrical resistivity parameter of the bit line material is changed from high-resistivity polysilicon/tungsten silicide to low-resistivity tungsten. This material substitution reduces electrical resistance by approximately 10 times, enabling faster charge discharge and improved device switching speed while maintaining process compatibility through adapted deposition and etching parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process steps, reduces sheet resistance of the bit line, and improves throughput by using low-resistance tungsten, addressing the limitations of existing techniques in nanoscale device fabrication.
Implementation Method 1
performing a CMP process to reduce surface roughness of the low-resistance tungsten layer
Implementation Method 2
etching a region of the first insulating layer, thus forming contact holes
Implementation Method 3
depositing a low-resistance tungsten layer on the entire surface including the contact holes
Data Source
AI summary
A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.