Array Substrate Shift Register Layout for Lower RC Loading
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Solution Overview
Problem
Existing display technologies face challenges in achieving uniform display brightness and narrow bezel designs due to resistance-capacitance (RC) loading in scanning signal lines, which results in insufficient charging time for sub-pixels and uneven display performance.
Innovation Solution
The array substrate design includes multiple groups of shift register circuits disposed in a non-edge region of the display area, with equal distances between them along the first direction, reducing RC loading and optimizing the distribution of scanning signals, and the use of fan-out structures on the second surface to facilitate control signal transmission without occupying the first surface, allowing for efficient scanning signal transmission and bezel-free designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shift register circuits are disposed only in edge regions, then device complexity is reduced, but RC loading in scanning signal lines increases resulting in insufficient charging time and non-uniform display brightness
Solution Approach 1:
The shift register circuits are divided into multiple groups disposed at different positions (edge regions and non-edge regions) along the first direction. Each group serves specific scanning signal lines, segmenting the overall shift register function across multiple locations to reduce RC loading on individual lines while maintaining systematic organization.
Solution Approach 2:
Different regions of the display area are assigned different shift register circuit configurations. Edge regions and non-edge regions both receive shift register circuits, but their positions and connections are optimized locally to address specific RC loading issues in different areas, ensuring uniform charging characteristics across the entire display.
2Loss of time
If multiple groups of shift register circuits are disposed in non-edge regions with equal distances, then RC loading is reduced and charging time is improved, but device complexity increases
Solution Approach 1:
The shift register circuits are segmented into multiple groups positioned at equal intervals in non-edge regions. This segmentation allows scanning signals to be distributed more evenly across the display area, reducing the effective length and RC loading of individual scanning signal lines, thereby improving charging time.
Solution Approach 2:
Shift register circuits are positioned in the non-edge regions (moving away from traditional edge-only placement) and arranged at equal distances along the first direction. This spatial reconfiguration in a different dimensional arrangement optimizes signal distribution and reduces RC loading effects.
3Area of stationary object
If fan-out structures are used on the second surface for control signal transmission, then the first surface remains clear for display and signal transmission efficiency improves, but device complexity increases
Solution Approach 1:
Fan-out structures are implemented on the second surface (back surface) of the substrate instead of the first surface. This moves control signal transmission pathways to another dimension (the opposite surface), keeping the first surface clear for optimal display area while enabling efficient signal distribution to shift register circuits.
Solution Approach 2:
The fan-out structures act as intermediary elements that receive control signals and distribute them to multiple shift register circuits. These intermediary structures are positioned on the second surface, mediating between the control signal sources and the shift register circuits while maintaining spatial separation from the display area on the first surface.
Data Source
AI summary
An array substrate includes a base substrate including a first surface, a plurality of scanning signal lines disposed on the first surface, and at least two groups of shift register circuits disposed in a display area of the first surface. The first surface has the display area. Each scanning signal line extends along a first direction. Each group of shift register circuits includes a plurality of shift register circuits arranged along a second direction. Each shift register circuit is coupled to a scanning signal line. The first direction and the second direction intersect. At least one group of shift register circuits is disposed in a non-edge region of the display area. The shift register circuit disposed in the non-edge region of the display area is configured to transmit a scanning signal to the scanning signal line at both sides of the shift register circuit along the first direction.