3D Memory Channel Layout With Top Gate Cuts for Smaller Memory Fingers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, necessitating a transition to three-dimensional (3D) memory devices to enhance memory density without increasing wafer size.
Innovation Solution
A method for forming a 3D memory device involves creating an alternating dielectric stack, forming temporary top selective gate cuts, and simultaneously constructing channel structures and top selective gate cut structures, allowing for reduced wafer size without compromising storage capacity by rearranging channel structures and optimizing the placement of top selective gate cuts between rows of channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar memory cell scaling is continued, then memory density improves, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory structure by stacking multiple oxide/nitride layers vertically. This dimensional change allows continued memory density improvement without the fabrication complexity penalties associated with further planar scaling, as the vertical stacking approach uses more manageable process steps.
Solution Approach 2:
The memory structure is segmented into multiple discrete oxide/nitride layer pairs stacked vertically, with each layer serving specific functional purposes. This segmentation allows independent optimization of each layer's properties and simplifies the fabrication process compared to attempting to scale planar cells further.
2Area of stationary object
If more oxide/nitride layers are stacked to improve area utilization, then wafer area utilization improves, but wafer size increases
Solution Approach 1:
Instead of increasing wafer size laterally to accommodate more memory structures, the patent stacks oxide/nitride layers in the vertical dimension. This allows high area utilization to be achieved without increasing the physical wafer footprint, as the capacity increase comes from vertical stacking rather than lateral expansion.
3Quantity of substance
If channel structures are arranged in staggered pattern with top selective gate cuts, then memory capacity is maintained, but memory finger area increases
Solution Approach 1:
The patent merges the formation of channel structures and top selective gate cuts into a unified process sequence. By integrating these previously separate fabrication steps, the design achieves compact arrangement where gate cuts are positioned between channel structures rather than requiring additional spacing, reducing overall memory finger area while preserving storage capacity.
Solution Approach 2:
The patent repositions top selective gate cuts in the vertical stacking sequence, placing them between specific oxide/nitride layer pairs rather than requiring lateral separation. This vertical arrangement allows channel structures to be more closely packed in the lateral direction, reducing memory finger area while maintaining the necessary gate functionality.
Data Source
AI summary
A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, a plurality of channel holes penetrating the alternating layer stack, a channel structure in each channel hole, and a top selective gate cut structure having a laminated structure and located between two rows of channel structures.