Deep Trench Capacitor Structure for Reduced Semiconductor Thickness
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Solution Overview
Problem
Conventional semiconductor structures with deep trench capacitors face challenges in achieving high density and low manufacturing costs due to the need for thick inter-level dielectric layers, which complicates the etching process and increases the total thickness of the semiconductor structure.
Innovation Solution
The semiconductor structure incorporates a deep trench capacitor design with a reduced inter-level dielectric layer thickness of approximately 9500 angstroms, achieved by lowering the top surface of the third conductive layer, allowing for easier etching and reduced manufacturing costs, and utilizes a polysilicon layer configuration with silicide and spacer formations to enhance electrical isolation and contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick inter-level dielectric layer is used in conventional deep trench capacitor structures, then electrical isolation is improved, but the total thickness of the semiconductor structure increases and etching complexity increases
Solution Approach 1:
The patent transitions from a thick inter-level dielectric layer approach to a deep trench capacitor design where the capacitor structure extends vertically into the substrate. This dimensional change allows electrical isolation to be achieved through the trench depth rather than through lateral dielectric thickness, thereby reducing the overall structure thickness while maintaining isolation performance.
Solution Approach 2:
The patent segments the capacitor structure into multiple components: a deep trench extending into the substrate, separate conductive plates positioned within and around the trench, and strategic dielectric layering. This segmentation allows each component to perform its function efficiently, achieving electrical isolation through the trench geometry rather than relying on a single thick dielectric layer.
2Reliability
If a thick inter-level dielectric layer is used in conventional deep trench capacitor structures, then electrical isolation is improved, but etching process complexity increases
Solution Approach 1:
The patent shifts the isolation mechanism from lateral dielectric thickness to vertical trench depth. This dimensional change simplifies the etching process because the trench can be formed to a controlled depth using standard deep trench etching techniques, avoiding the need to etch through or manage extremely thick dielectric layers laterally.
Solution Approach 2:
The patent performs preliminary actions by forming the deep trench and positioning the conductive plates before final dielectric layer deposition. This sequence allows the trench geometry to establish the isolation framework early in the process, simplifying subsequent steps and reducing overall process complexity compared to managing thick dielectric layers throughout the fabrication sequence.
3Length of stationary object
If the top surface of the third conductive layer is lowered, then inter-level dielectric layer thickness is reduced and manufacturing cost decreases, but electrical isolation must be maintained
Solution Approach 1:
The patent compensates for reduced dielectric thickness by increasing the vertical dimension of the trench and adjusting the positioning of conductive plates. The isolation function is transferred from the lateral dielectric layer thickness to the vertical trench depth and plate configuration, allowing thin dielectric layers to suffice while maintaining electrical isolation through the three-dimensional geometry.
Solution Approach 2:
The patent applies different dielectric materials or thicknesses at different locations within the structure. By strategically positioning conductive plates and varying dielectric properties in specific regions, the design achieves effective electrical isolation even with reduced overall dielectric layer thickness, optimizing both cost and performance.
Data Source
AI summary
The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed on a bottom surface and sidewall surfaces of a filled trench of the substrate. A first conductive layer is disposed on the first dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A second dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the second dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A third dielectric layer is disposed on the second conductive layer. A third conductive layer is disposed in the filled trench and on the third dielectric layer. A top surface of the third conductive layer is lower than the second surface of the second conductive layer.