Semiconductor Switching Device Isolation via Gate Extensions
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Solution Overview
Problem
Existing methods for isolating circuit components from photo-sensitive devices in semiconductor fabrication, such as shallow trench isolation and doped semiconductor material techniques, are either damaging to the substrate or less effective in preventing dark currents and white pixel effects, which affect light intensity measurements.
Innovation Solution
The use of a device isolation structure with a gate structure having extensions that partially enclose the source/drain regions, limiting ion implantation doping and preventing leakage into the active region of photodiodes, and the formation of device isolation structures into the semiconductor substrate to create a junction that isolates the circuitry from the photodiodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation is used to isolate circuit components from photo-sensitive devices, then isolation effectiveness is improved, but substrate surface is damaged by plasma etching
Solution Approach 1:
The patent changes the isolation method from shallow trench isolation (STI) to device isolation, altering the fundamental parameter of isolation technique. Device isolation uses doped semiconductor material with different doping concentrations to form junctions, avoiding plasma etching entirely while maintaining isolation effectiveness between circuit components and photo-sensitive devices
Solution Approach 2:
The patent replaces the mechanical plasma etching process with a chemical doping process. Instead of physically removing material through plasma etching to create isolation trenches, the invention uses ion implantation or diffusion to create doped regions that form isolation junctions, eliminating substrate surface damage while achieving the same isolation function
2Object-affected harmful factors
If doped semiconductor material is used for device isolation, then substrate surface damage is avoided, but isolation effectiveness against source/drain regions is reduced
Solution Approach 1:
The patent applies local quality by creating regions with different doping concentrations in specific locations. The device isolation structure has a first doping concentration that forms junctions with adjacent semiconductor regions having a second doping concentration. This localized variation in doping concentration creates effective isolation at the interface while maintaining the benefits of device isolation throughout the structure
Solution Approach 2:
The patent creates a composite isolation structure by combining doped semiconductor material with different doping concentrations. The device isolation structure comprises a first doped semiconductor material with a first doping concentration, adjacent to a second doped semiconductor material with a second doping concentration, forming a composite structure that enhances isolation effectiveness while avoiding plasma etching damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively isolates circuit components from photodiodes, reducing dark currents and white pixel effects, thereby improving the accuracy of light intensity measurements without damaging the substrate.
Implementation Method 1
This technique involves the formation of a doped semiconductor material instead of a dielectric material. The doped semiconductor material is of a different concentration than the doping concentration of adjacent semiconductor materials, thus forming a junction.
Implementation Method 2
limiting ion implantation doping and preventing leakage into the active region of photodiodes
Data Source
AI summary
A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.