Multi-Plug Memory Device Link Segmentation for Integration Density
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Solution Overview
Problem
The miniaturization of electronic apparatuses is limited by the physical constraints of semiconductor device integration density, which cannot be infinitely increased due to nano-level line width processing limitations, necessitating the development of multi-bit semiconductor devices to enhance storage capacity.
Innovation Solution
A memory device utilizing a link and anode structure connected by multiple plugs, allowing for varying electrical resistance and multi-bit data storage by selectively contacting plugs with applied voltage, enabling the storage of multiple data states without increasing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor techniques with nano-level line width processing are used, then manufacturing precision is improved, but integration density cannot be infinitely increased due to physical limitations
Solution Approach 1:
The link is divided into multiple segments, each connected to a separate plug. By selectively forming voids in different link segments, the device can represent multiple data states (0, 1, 2, 3) without requiring proportionally wider line widths, thus maintaining manufacturing precision while increasing storage capacity per device.
Solution Approach 2:
The patent transitions from storing one bit per device to storing multi-bit data (2 bits) in a single device by adding vertical dimensionality through multiple plugs and link segments. This allows integration density to increase without requiring narrower line widths, overcoming the physical limitations of conventional scaling.
2Device complexity
If a semiconductor device stores only one bit data, then device simplicity is maintained, but integration density cannot be doubled even if replaced by multi-bit devices
Solution Approach 1:
The link is segmented into multiple portions, each associated with a different plug. This segmentation enables multi-bit storage capability while maintaining a relatively simple overall device structure that can be manufactured using conventional semiconductor processes, thus not excessively increasing device complexity.
Solution Approach 2:
Multiple plugs and link segments are nested within a single memory device footprint. This nesting allows multi-bit storage capacity to be achieved without proportionally increasing the device area, thereby increasing integration density without linearly increasing structural complexity.
3Productivity
If multiple plugs are used to enable multi-bit storage, then integration density is increased, but device structure becomes more complex
Solution Approach 1:
Multiple plugs and link segments are merged into a single integrated memory device structure. This merging achieves multi-bit storage capability and increased integration density while consolidating the complexity into a unified device architecture rather than requiring separate devices for each bit.
Solution Approach 2:
The link structure serves multiple functions: it connects different plugs, stores multi-bit data through selective void formation, and enables both reading and writing operations. This multi-functionality reduces the need for additional separate components, thereby increasing integration density without proportionally increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased integration density and efficient data storage in a compact form, enabling the storage of multiple bits of data using a single device, thereby overcoming the limitations of conventional semiconductor miniaturization.
Implementation Method 1
The link may vary an electrical resistance between the cathode and the anode by selectively contacting one or more of the plurality of plugs based on a voltage applied between the cathode and the anode
Data Source
AI summary
A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.