Display Panel Nano-Groove Planarization for 3D OLED Mura Reduction

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Solution Overview

Problem

Current 3D OLED display technologies suffer from severe Mura abnormality and short-circuit issues due to limitations in nano-scale gap formation between sub-pixels, leading to poor display quality and cathode disconnection.

Innovation Solution

A display panel design featuring a planarization layer with nano-scale grooves and sub-pixels with a nano-scale second gap between electrodes, where the orthographic projection of the gap on the array substrate is within the groove projection, along with a pixel defining layer forming an isolation plug to prevent Mura abnormality and ensure smooth electrode arrangement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional OLED structure is used for 3D display, then 3D display function is achieved, but severe Mura abnormality and cathode short-circuit occur

Engineering Contradiction:
Improve3D display functionVSAvoiddisplay quality and cathode connection
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The invention divides each sub-pixel into multiple secondary sub-pixels arranged in different layers, with each layer containing specific secondary sub-pixels. This segmentation enables 3D display functionality while maintaining proper cathode connection and avoiding Mura abnormality through the specific arrangement pattern.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from traditional 2D OLED display to 3D display by arranging secondary sub-pixels in multiple layers along the vertical dimension. Different layers are positioned at different depths, enabling stereoscopic display while solving the cathode short-circuit issue through proper spatial separation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If nano-scale gap formation is attempted between sub-pixels, then 3D display resolution is improved, but manufacturing precision requirements become extremely high

Engineering Contradiction:
Improvegap size controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The invention forms the planarization layer with embedded nano-scale grooves before forming the electrode patterns. This preliminary action defines the gap positions and dimensions through the groove structures, making subsequent electrode formation easier and reducing the overall manufacturing precision requirements.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The planarization layer with nano-scale grooves serves as an intermediary structure that pre-defines the gap regions. This intermediary layer simplifies the electrode formation process by providing physical guides for gap placement, reducing the direct precision requirements between adjacent electrodes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If multiple patterning steps are used to form electrodes, then electrode precision is improved, but manufacturing complexity and resource usage increase

Engineering Contradiction:
Improveelectrode positioning accuracyVSAvoidnumber of patterning steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The planarization layer with pre-formed nano-scale grooves performs the preliminary action of defining gap positions. This allows subsequent electrode patterns to be formed with simpler patterning steps, as the groove structures already establish the required spatial relationships and positioning accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11711948B2Display panel, preparation method thereof, and display apparatus
Publication Date: 2023.07.25 BOE TECHNOLOGY GROUP CO LTD
  • US11711948B2 patent drawing
  • US11711948B2 patent drawing
  • US11711948B2 patent drawing

AI summary

The present disclosure relates to the field of display technology, and proposes a display panel, a preparation method thereof, and a display apparatus. The display panel includes an array substrate, a planarization layer group, and a plurality of sub-pixels. The array substrate includes a switch array formed by a plurality of switch units. The planarization layer group is provided on the array substrate, and nano-scale grooves are provided on the planarization layer group. The sub-pixels are provided on a side of the planarization layer group away from the array substrate. The sub-pixel includes a plurality of first electrodes, wherein the first electrode is connected to the switch unit of the array substrate, a nano-scale second gap is provided between two adjacent first electrodes, and an orthographic projection of the second gap on the array substrate is located within an orthographic projection of the groove on the array substrate.