Vertical Gate Memory Device P-type Semiconductor Pattern Erase Speed
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face challenges in efficient erase operations due to low erase speed and high resistance of source lines, particularly in vertical gate-type devices where GIDL current is used, limiting their performance.
Innovation Solution
A vertical gate-type non-volatile memory device is designed with a P-type impurity-doped region, interlayer insulating layers, and a P-type semiconductor pattern that contacts the sidewalls of channel layers, allowing for direct injection of holes during erase operations and reducing source line resistance by connecting source lines to a low-resistance gate or metal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GIDL current is used for erase operation in vertical gate-type devices, then erase operation can be performed, but erase speed and efficiency are low
Solution Approach 1:
The patent changes the electrical parameters by introducing a P-type impurity-doped region in the substrate and forming a P-type semiconductor pattern that contacts the channel layers. This allows applying high positive voltage to inject holes directly into the gate through Fowler-Nordheim tunneling, transforming the erase mechanism from GIDL-based to direct hole injection, thereby improving both erase speed and efficiency
Solution Approach 2:
The P-type semiconductor pattern acts as an intermediary structure between the P-type impurity-doped region and the channel layers. It facilitates the injection of holes into the gate during erase operations by providing a conductive path, enabling efficient charge transfer without relying on GIDL current
2Productivity
If the number of strings connected to source lines increases, then integration density is improved, but resistance of source lines increases
Solution Approach 1:
The patent segments the source line connection by introducing a P-type semiconductor pattern that contacts the sidewalls of multiple channel layers at different heights. This creates multiple contact points along the source line, effectively dividing the single high-resistance path into multiple lower-resistance segments, thereby reducing overall source line resistance while maintaining high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient erase operations and reduces source line resistance, enhancing the overall performance of three-dimensional non-volatile memory devices by improving erase efficiency and integration density.
Implementation Method 1
an erase operation may not be performed by applying a high positive voltage to a substrate body having a high-concentration P-type impurity region to inject holes into a gate of the memory cell by Fowler-Nordheim Tunneling
Implementation Method 2
a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region
Data Source
AI summary
A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.