Unified DRAM-Logic Bridge With Matched I/O Voltage Levels
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Solution Overview
Problem
The scaling of DRAM technology has slowed down due to challenges in integrating 3D transistor structures, leading to a performance gap with logic chips, known as the memory-wall effect, which affects data transfer rates and energy efficiency, and existing solutions like high-bandwidth DRAM face manufacturing difficulties and high costs.
Innovation Solution
A unified micro system with a base DRAM chip and a logic chip, both using fin-structured transistors, where the DRAM chip includes a DRAM bridge area with third fin-structured transistors and I/O pads, and the logic chip includes a logic bridge area with second fin-structured transistors, allowing for direct electrical coupling without voltage conversion, enabling seamless data flow and reducing the memory-wall effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM technology uses conventional planar transistor structures, then manufacturing process is simpler, but performance and leakage control are insufficient
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to 3D fin-structured transistors. This dimensional change enables better gate control over the channel, significantly improving leakage control and device performance while maintaining compatibility with existing manufacturing processes through adapted fabrication steps.
Solution Approach 2:
The patent modifies key transistor parameters including introducing fin height as a new dimensional parameter, adjusting channel width and length ratios, and optimizing doping profiles. These parameter changes enable superior electrical characteristics and leakage control compared to planar structures.
2Adaptability or versatility
If DRAM and logic chips use different transistor structures, then each can be optimized independently, but voltage incompatibility and interface complexity increase
Solution Approach 1:
The patent employs the same fin-structured transistor design in both DRAM and logic chips, creating a universal transistor architecture. This enables voltage compatibility between the two chip types and simplifies the interface design, as both chips operate at compatible voltage levels and use similar transistor characteristics.
Solution Approach 2:
By using identical fin-structured transistor designs in both DRAM and logic components, the patent creates homogeneity in the electrical characteristics across the system. This reduces interface complexity and enables seamless integration without requiring voltage conversion or specialized interface circuits.
3Productivity
If DRAM scaling continues at traditional pace, then manufacturing remains manageable, but performance gap with logic chips widens
Solution Approach 1:
The patent uses 3D fin-structured transistors to achieve higher transistor density and performance in DRAM devices, enabling data transfer rates that match logic chip speeds. This dimensional transition allows DRAM to keep pace with logic chip scaling without requiring overly complex manufacturing processes.
4Quantity of substance
If high-bandwidth DRAM is implemented with stacked capacitors, then memory capacity increases, but manufacturing difficulty and cost increase
Solution Approach 1:
The patent implements stacked capacitor structures that extend vertically in the third dimension, increasing memory capacity within the same footprint. This 3D stacking approach efficiently increases storage density while maintaining compatibility with the finFET manufacturing process, avoiding the need for overly complex fabrication steps.
Data Source
AI summary
An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.