3D Memory Stair-Step Layout for Direct Conductor Tier Access
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Solution Overview
Problem
Current memory circuitry technologies face challenges in efficiently forming memory arrays with vertically-stacked memory cells, particularly in achieving precise electrical coupling and structural integrity through the stair-step structure, which affects the performance and reliability of memory cells.
Innovation Solution
The method involves forming a stack with vertically-alternating conductive and insulative tiers, creating stair-step structures with opposing flights of stairs, and using imageable and non-imageable resist layers to define the stair-step structures, allowing for direct electrical coupling and anchoring of channel material to the conductor tier, thereby ensuring reliable access to memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stair-step structures are used with uniform depths, then manufacturing simplicity is maintained, but electrical access efficiency and circuit element optimization are compromised
Solution Approach 1:
The patent applies local quality by creating stair-step structures with varying horizontal depths at different locations. Specifically, some stairs have a first horizontal depth while others have a second horizontal depth that is greater than the first, allowing optimization of electrical access at specific positions without uniformly increasing complexity throughout the entire structure.
Solution Approach 2:
The patent introduces dimensional variation by extending stairs in multiple directions with different horizontal depths. This creates a multi-dimensional stair-step structure where conductive vias can access conductor tiers at different horizontal positions, improving electrical access efficiency through spatial optimization rather than simply increasing vertical stacking.
2Quantity of substance
If multiple conductor tiers are stacked vertically to increase memory capacity, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the formation process into alternating etching and lateral-trimming steps. This segmentation allows incremental creation of the multi-tier stack structure, where each cycle deposits and patterns a portion of the conductor tier and insulator layer, reducing the precision burden on any single manufacturing step while enabling high vertical stacking.
Solution Approach 2:
The patent employs preliminary patterning actions where masks are formed to define the stair-step structures before final etching. This preliminary action establishes the horizontal depth variations and stair configurations in advance, guiding subsequent manufacturing steps to achieve the complex multi-tier structure with reduced real-time precision requirements.
3Ease of operation
If alternating etching and lateral-trimming steps are used to create varying stair depths, then electrical access optimization is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent introduces masks as intermediary elements that facilitate the alternating etching and lateral-trimming process. These masks temporarily define the horizontal boundaries of stairs at different depths, enabling precise electrical access optimization without requiring complex direct patterning methods. The masks are removed after transferring the pattern, simplifying the overall manufacturing approach.
Solution Approach 2:
The patent employs periodic alternating cycles of etching and lateral-trimming operations to create the varying stair depths. This periodic action systematically builds the multi-depth structure through repeated patterned processing steps, making the complex manufacturing process more manageable and controllable through rhythmical, repeatable operations.
Data Source
AI summary
Memory circuitry comprising strings of memory cells comprises channel-material strings of memory cells extending through insulative tiers and conductive tiers in a memory-array region. The insulative and conductive tiers extend from the memory-array region into a stair-step region. A plurality of stair-step structures is in the stair-step region. The stair-step structures individually comprise two opposing flights of stairs. The stair-step structures comprise an SGD stair-step structure and non-SGD stair-step structures. At least one of the non-SGD stair-step structures has less total stairs than are in individual of multiple others of the non-SGD stair-step structures. Other embodiments, including method, are disclosed.