3D IC Cell Placement via Tiered 2D-to-3D Swapping
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Solution Overview
Problem
Further improvements in integrated circuit density are difficult to achieve within the limitations of two-dimensional layouts, prompting the need for three-dimensional integrated circuits (3D ICs) that vertically stack semiconductor bodies and require efficient methods for cell placement and routing across multiple tiers.
Innovation Solution
A system and method for placing and routing 3D ICs that involves partitioning 2D cells into tiers, swapping them with corresponding 3D cells from specialized libraries, and performing global placement to optimize cell location and interconnect structure across multiple layers, using electronic design automation tools to manage the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional layout is used, then design simplicity is maintained, but integrated circuit density cannot be further improved
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional integrated circuit architecture by vertically stacking multiple semiconductor dies (first die, second die, third die) connected through interconnect layers. This dimensional change enables significantly higher component density while managing complexity through systematic tiered organization and automated placement algorithms that handle the increased spatial arrangement.
2Quantity of substance
If three-dimensional stacked layout is implemented, then component density is increased, but cell placement and routing complexity increases
Solution Approach 1:
The patent divides the three-dimensional IC into distinct tiers (first tier with first die, second tier with second die, third tier with third die), where each tier contains specific functional blocks. This segmentation allows independent design and optimization of each layer while maintaining overall system functionality, reducing the complexity of placing and routing cells across the entire three-dimensional structure.
Solution Approach 2:
The patent employs automated placement algorithms that perform preliminary cell placement and routing calculations before physical fabrication. The system pre-calculates optimal cell positions and interconnect paths for all three tiers, managing the complexity through computational preparation rather than manual arrangement during manufacturing.
3Quantity of substance
If vertical stacking of semiconductor bodies is performed, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediate interconnect layers and bonding interfaces between the vertically stacked semiconductor dies. These intermediary structures serve as precision alignment references and mechanical buffers, facilitating accurate vertical alignment and reducing the direct manufacturing precision burden on the final stacked configuration.
Data Source
AI summary
A method is disclosed. The method includes: obtaining a circuit design including a plurality of 2D cells of a 2D cell library; partitioning the plurality of 2D cells of the circuit design into a first group assigned to a first tier and a second group assigned to a second tier; swapping the 2D cells assigned to the first tier with corresponding 3D cells of a first type 3D cell library respectively; and swapping the 2D cells assigned to the second tier with corresponding 3D cells of a second type 3D cell library respectively; wherein at least one of the obtaining, partitioning, and swapping is performed using a processor. An associated system is also disclosed.