Configuration CAD TRIZ Cases
- Continuous PVT Timing Prediction via Distance-Based Corner Selection
A corner prediction system selects trained PVT corners using distance metrics to generate performance metric values for target operating conditions.
- Automated PCell Layout Verification in EDA Software
Electronic design automation software generates schematic and layout variants from parameterized cell definitions to accelerate analog integrated circuit workflows.
- Circuit Diagram Search via Graph Similarity
Convert circuit diagrams into graph structures to calculate similarity and resolve connection information analysis bottlenecks.
- Overlay Control Model for Semiconductor Wafer Sampling
A computer-generated selection model optimizes wafer and field sampling points for overlay error measurement.
- 3D IC Cell Placement via Tiered 2D-to-3D Swapping
Partitioning 2D cells into tiers and swapping them with specialized 3D components reduces layout complexity while increasing integration density.
- NoC Topology Synthesis via Segmented Phases
Segmenting NoC synthesis into abstract and refinement phases resolves the accuracy versus computation time trade-off for complex SoC designs.
- Effective Cell Approximation for Non-Periodic Logic Metrology
A periodic effective cell approximation models non-periodic logic structures for optical metrology.
- EM Analysis of Integrated Circuit Metal Lines
EDA tools analyze electromigration data in metal lines to detect hotspots and modify connecting paths.
- Capacitor Arrangement Assisting Device for Power Supply Impedance
A capacitor arrangement assisting device calculates maximum allowable wiring length based on target impedance and equivalent series inductance.
- Hyperparameter Partitioning for Deep Reinforcement Learning IC Design
A deep reinforcement learning system partitions integrated circuit netlists into balanced sub-graphs to reduce computational load.
- Semiconductor Power Supply Wiring Notches Reduce Parasitic Capacitance
Notched power supply wirings minimize parasitic capacitances at signal intersections while maintaining mesh coverage and stabilizing potentials.
- Static Timing Analysis Controller for Integrated Circuits
A static timing analysis controller identifies invariable flip flop feedback loops within integrated circuit designs.
- Circuit Latency Equivalence Verification via Flip-Flop Annotation
A verification system determines latency change values for circuit pins by inserting or removing flip-flops to calculate total pin latency.
- Integrated Circuit Timing Analysis via Parasitic Extraction
A computer-implemented method extracts delay variation data from timing arcs to optimize integrated circuit design.
- Unified Verification Coverage Model for Multi-Engine Data Merging
A unified verification coverage model merges data from multiple engines into a single coherent metric.
- Virtual Layout OPC Verification for Semiconductor Mask Design
Optical proximity correction on a virtual layout reduces pattern formation errors and shortens development time.