Overlay Control Model for Semiconductor Wafer Sampling

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Solution Overview

Problem

Current methods for overlay control and monitoring in semiconductor integrated circuit manufacturing rely heavily on human experience, leading to inefficient and ineffective processes due to poor measurement coverage and redundant measurements, resulting in low throughput and increased complexity.

Innovation Solution

A system that includes a computer-generated selection model for selecting points, fields, and wafers for overlay error measurement, using statistical analysis to optimize sampling and generate a combined overlay correction map, which adjusts exposure tool parameters to reduce overlay errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If user experience-based sampling is used for overlay measurement, then measurement process is simple to implement, but measurement coverage is poor and contains redundant measurements

Engineering Contradiction:
Improveoverlay measurement coverageVSAvoidsampling strategy complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent transforms the sampling strategy from static user experience-based selection to dynamic model-based selection. The computer-generated selection model uses parameters such as overlay error sensitivity, measurement location coordinates, and statistical metrics to dynamically determine optimal sampling points, fields, and wafers. This parameter-driven approach replaces subjective human judgment with objective, data-driven decisions, improving measurement coverage while eliminating redundancy.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where overlay measurement results are continuously fed back into the selection model. The model uses historical overlay error data, measurement results, and process parameters to iteratively refine and update sampling strategies. This closed-loop feedback system ensures that sampling locations are continuously optimized based on actual process performance, improving measurement effectiveness without requiring increased complexity in the sampling procedure.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If comprehensive overlay measurement is performed across all wafers and locations, then measurement coverage is complete, but process complexity and time increase significantly

Engineering Contradiction:
Improveoverlay measurement coverageVSAvoidmeasurement time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts only the most critical measurement information needed for overlay control by using the computer-generated selection model to identify and measure only at high-value sampling locations. Instead of measuring all wafers and all locations, the model extracts key overlay error signals from strategically selected sampling points, fields, and wafers. This selective extraction approach maintains adequate measurement coverage while dramatically reducing the total number of measurements required, thereby reducing measurement time and process complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If more sampling locations are measured on each wafer, then measurement coverage improves, but throughput decreases due to increased measurement time

Engineering Contradiction:
Improvemeasurement coverageVSAvoidmanufacturing throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies partial action by measuring only at the necessary number of sampling locations rather than all possible locations. The computer-generated selection model determines the optimal subset of sampling points, fields, and wafers that provide sufficient overlay error information with minimal measurements. This partial measurement approach achieves adequate measurement coverage for process control while maintaining high manufacturing throughput by avoiding excessive measurements at non-critical locations.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10866524B2Method and system for overlay control
Publication Date: 2020.12.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10866524B2 patent drawing
  • US10866524B2 patent drawing
  • US10866524B2 patent drawing

AI summary

A method includes selecting a group of wafers, each of the wafers having a resist pattern; selecting a group of fields for each of the wafers; selecting one or more points on each of the fields; measuring overlay errors on the resist pattern at locations associated with the one or more points selected on the respective wafers; and generating a combined overlay correction map based on measurements of the overlay errors on the wafers. At least one of the selecting of the group of wafers, the selecting of the group of fields, and the selecting of the one or more points is based on a computer-generated model.