Circuit Latency Equivalence Verification via Flip-Flop Annotation
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Solution Overview
Problem
Verifying latency equivalence in integrated circuit designs is complex, especially during retiming and pipelining operations, due to changes in flip-flop positions, making it difficult to detect and correct latency imbalances in a computationally efficient manner.
Innovation Solution
A system that determines latency change values for pins of circuit components by inserting or removing flip-flops, calculates total latency, and compares it to detect mismatches, allowing for the detection and automatic correction of latency errors, thereby ensuring latency equivalence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal verification is performed for retiming operations with elaborate flip-flop mapping rules, then latency equivalence can be verified, but the complexity of creating and applying these rules increases significantly
Solution Approach 1:
The patent extracts the complex flip-flop mapping rules from the verification process and replaces them with a simpler annotation-based system. Instead of requiring elaborate rules to track flip-flop positions through retiming, the system uses direct latency annotations on circuit elements, which are automatically propagated and verified without complex transformation rules.
Solution Approach 2:
The patent creates a simplified copy of the circuit design with latency annotations that mirror the original design's timing characteristics. This annotated copy is then used for verification purposes, avoiding the need to apply complex retiming rules to the original design while maintaining verification accuracy.
2Measurement precision
If simulation is used for pipelining functional equivalence checking, then latency behavior can be verified, but the verification process becomes time-consuming
Solution Approach 1:
The patent performs preliminary latency annotation on circuit elements before verification. By pre-computing and storing latency values on each element, the system avoids time-consuming simulation during the actual verification process. The annotations are propagated through the circuit design in advance, enabling rapid equivalence checking.
Solution Approach 2:
The patent replaces the mechanical simulation process with a static analysis approach based on latency annotations. Instead of dynamically simulating signal propagation through the circuit, the system uses pre-computed latency values and mathematical propagation rules to verify timing equivalence, dramatically reducing verification time.
3Reliability
If comprehensive flip-flop tracking is implemented during retiming, then latency changes can be monitored, but the computational complexity increases due to cascades of deleted and inserted flip-flops
Solution Approach 1:
The patent introduces latency annotations as an intermediary representation that mediates between the original circuit design and the verification process. These annotations serve as a simplified model that captures essential timing information without requiring detailed tracking of individual flip-flop transformations during retiming operations.
Data Source
AI summary
Verifying a circuit design may include, in response to modification of the circuit design involving at least one of inserting or removing a flip-flop, determining, using computer hardware, latency change values for pins of components of the circuit design, determining, using the computer hardware, total latency for the pins of the components of the circuit design based, at least in part, upon the latency change values, and comparing, using the computer hardware, total latency of the pins of the components of the circuit design. Verifying the circuit design may also include detecting, using the computer hardware, a latency error within the circuit design based upon the comparing and generating, using the computer hardware, a notification of the latency error in the circuit design, wherein the notification specifies a type of the latency error detected.