Static Timing Analysis Controller for Integrated Circuits
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Solution Overview
Problem
Static timing analysis tools often overestimate timing violations in integrated circuit designs, leading to unnecessary buffer additions, which increase the design size and complexity.
Innovation Solution
The implementation of a static timing analysis controller that identifies and ignores invariable flip flop feedback loops, thereby refraining from calculating propagation delays and adding buffers to these loops, resulting in a more accurate analysis and optimized design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If static timing analysis tools calculate propagation delays for all flip flop feedback loops, then timing violations are identified, but the number of false violations increases and design size increases due to unnecessary buffer additions
Solution Approach 1:
The patent extracts and removes invariable flip flop feedback loops from the timing analysis scope. The STA tool identifies these specific loops and excludes them from propagation delay calculations, thereby eliminating false timing violation detections and preventing unnecessary buffer additions while maintaining analysis accuracy for legitimate timing issues
Solution Approach 2:
The patent applies different analysis quality to different parts of the circuit. Invariable feedback loops are treated with a simplified analysis model that ignores propagation delays, while the rest of the circuit undergoes full rigorous timing analysis. This localized differentiation resolves the contradiction by applying precise analysis only where needed
2Reliability
If buffers are added to fix all identified hold violations, then timing constraints are met, but the IC design becomes larger than necessary
Solution Approach 1:
The patent extracts false hold violations arising from invariable feedback loops and removes them from the set of violations requiring buffer insertion. By excluding these loops from timing analysis, the tool avoids generating false violation reports and consequently prevents the addition of unnecessary buffers to the design
Solution Approach 2:
The patent changes the analysis parameter for invariable feedback loops by setting propagation delay to zero or ignoring it entirely. This parameter modification causes the timing analysis to not detect hold violations in these loops, thereby eliminating the trigger for buffer addition while maintaining reliability for actual timing issues
Data Source
AI summary
A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.