Integrated Circuit Timing Analysis via Parasitic Extraction
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased wire process variations, causing resistance and capacitance changes in metal layers, which result in clock delays and timing violations, making conventional timing analysis complex and time-consuming due to large parasitic component description files.
Innovation Solution
A computer-implemented method and system for designing integrated circuits that involves receiving layout data and technology files to generate parasitic component data by extracting delay variation data from timing arcs, allowing for efficient timing analysis and optimization of wire delays and capacitance sensitivity coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional parasitic component description files include resistance sensitivity and capacitance sensitivity for each node, then timing analysis can be performed, but the size of the parasitic component description file becomes very large and the complexity and time required for calculation greatly increase
Solution Approach 1:
The patent extracts only the necessary parasitic component data (resistance sensitivity and capacitance sensitivity) for nodes that are actually involved in timing paths, rather than including data for all nodes in the circuit. This selective extraction reduces the size of parasitic component description files and decreases calculation complexity while maintaining timing analysis accuracy for critical paths.
Solution Approach 2:
The patent segments the timing analysis process by identifying and analyzing only the relevant timing paths and their associated parasitic components, rather than performing comprehensive analysis on the entire circuit. This segmentation allows focusing computational resources on critical paths where timing violations are most likely to occur.
2Reliability
If comprehensive parasitic component data is included for all nodes, then timing analysis coverage is complete, but the file size becomes very large and processing time increases
Solution Approach 1:
The patent extracts parasitic component data selectively based on timing path relevance. By identifying nodes that lie on critical timing paths and extracting parasitic data only for those nodes, the method maintains comprehensive coverage of timing-critical areas while significantly reducing file size and processing time compared to including all nodes.
Solution Approach 2:
The patent applies partial action by performing parasitic extraction and timing analysis only on the subset of nodes and paths that are critical for timing performance, rather than exhaustively analyzing the entire circuit. This partial approach achieves sufficient reliability for timing validation while reducing processing time.
3Reliability
If wire process variations are considered in timing analysis, then timing constraint violations can be identified, but the analysis complexity and computational requirements increase
Solution Approach 1:
The patent applies local quality by considering wire process variations (resistance and capacitance deviations from nominal values) specifically at nodes and segments along timing paths, rather than uniformly across the entire circuit. This localized consideration of process variations identifies timing constraint violations while maintaining manageable analysis complexity.
Solution Approach 2:
The patent changes parameters by introducing resistance sensitivity and capacitance sensitivity values that represent process variations. By incorporating these parameter variations into the timing analysis model, the method can identify timing constraint violations under different process conditions while maintaining a systematic approach to managing analysis complexity.
Data Source
AI summary
A computer-implemented method and a computing system for designing an integrated circuit are provided. The computer-implemented method of designing an integrated circuit includes receiving layout data for the integrated circuit and a technology file that includes corners of a parasitic component of each of a plurality of layers included in the integrated circuit, generating parasitic component data by performing a parasitic component extraction operation on corners of a parasitic component of a layer in a timing arc on a net of the integrated circuit, the parasitic component data including delay variation data of the timing arc, and generating timing analysis data by performing a timing analysis on the integrated circuit, based on the parasitic component data.