Virtual Layout OPC Verification for Semiconductor Mask Design
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Solution Overview
Problem
The existing semiconductor manufacturing processes face inefficiencies due to the time-consuming and error-prone nature of optical proximity correction and mask design, which can lead to issues in pattern formation and increased development time.
Innovation Solution
The method involves creating a virtual layout by randomly placing and routing standard cells, performing optical proximity correction, and verifying the mask, allowing for the modification of the layout and optical proximity correction model based on verification results to improve accuracy and reduce development time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If optical proximity correction and mask design are performed using traditional methods, then the process follows conventional design rules, but the development time is extended and errors are more likely to occur
Solution Approach 1:
The patent applies preliminary action by performing optical proximity correction verification on a virtual layout before finalizing the actual layout design. This allows potential errors to be detected and corrected in advance, reducing development time and improving reliability of the final design
Solution Approach 2:
The patent creates a virtual layout that copies the structure and characteristics of the actual layout to be designed. This virtual copy is used for preliminary OPC verification, allowing errors to be identified without affecting the actual design timeline, thus reducing overall development time while improving reliability
2Manufacturing precision
If optical proximity correction is performed on the actual layout, then the design is finalized, but time-consuming iterations and errors may occur requiring rework
Solution Approach 1:
The patent performs optical proximity correction verification on a virtual layout before finalizing the actual layout. This preliminary verification ensures pattern formation accuracy is validated in advance, eliminating the need for time-consuming iterations and rework on the actual design, thus improving both manufacturing precision and productivity
Solution Approach 2:
The patent implements a feedback mechanism where the results of OPC verification on the virtual layout are used to identify and correct potential pattern formation issues before applying the same OPC parameters to the actual layout. This feedback loop ensures high manufacturing precision without requiring iterative rework, thereby improving development efficiency
3Productivity
If a virtual layout is created and verified before actual design, then development time is reduced and errors are minimized, but additional verification steps are required
Solution Approach 1:
The patent creates a virtual layout that replicates the key structural characteristics of the actual layout. This copy is used for preliminary OPC verification, allowing the system to validate pattern formation accuracy without requiring complex iterative processes on the actual design, thus improving productivity while keeping the additional process steps manageable
Solution Approach 2:
The virtual layout serves multiple functions: it acts as a test model for OPC verification, a validation tool for pattern formation accuracy, and a reference for optimizing the actual design. This multi-functionality justifies the additional verification step by providing comprehensive validation that improves development efficiency without requiring proportionally complex processes
Data Source
AI summary
A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.