EM Analysis of Integrated Circuit Metal Lines
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Solution Overview
Problem
Traditional electromigration (EM) analysis tools are inadequate in detecting and addressing EM phenomena in lower metal layers of integrated circuits, particularly on cell output pins, due to increasing current density and shrinking wire dimensions, which can lead to IC failure.
Innovation Solution
The use of electronic design automation (EDA) tools to analyze and modify interconnecting paths and cell structures within integrated circuits, including moving or adding connecting paths and vias to redistribute current and alleviate EM hotspots, thereby reducing current density and preventing EM-induced failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wire dimensions are shrunk to increase integration density, then device miniaturization is achieved, but current density increases leading to electromigration in lower metal layers
Solution Approach 1:
The patent applies local quality by making cell output pins visible and accessible only at strategic locations where they can be effectively monitored for electromigration. This localized visibility approach allows EM analysis to focus on critical areas without requiring full visibility of all lower metal layer structures, thereby maintaining reliability assessment capability while working within miniaturized device constraints.
Solution Approach 2:
The patent transitions from traditional two-dimensional planar EM analysis to a three-dimensional approach by enabling visibility of cell output pins through the metal layers. This dimensional change allows EM hotspots to be detected and analyzed in lower metal layers that were previously inaccessible, providing comprehensive EM assessment despite device miniaturization.
2Measurement precision
If traditional EM analysis tools are used, then higher metal layers are effectively analyzed, but lower metal layers and cell output pins cannot be detected
Solution Approach 1:
The patent implements universality by developing an EM analysis tool that can simultaneously analyze multiple metal layers including lower layers and cell output pins that were previously inaccessible. The tool maintains its effectiveness for higher metal layer analysis while extending capability to lower layers, providing a unified multi-functional EM analysis solution across all metal layers.
Solution Approach 2:
The patent applies local quality by making cell output pins visible and accessible only at strategic locations where they can be effectively monitored for electromigration. This localized visibility approach allows EM analysis to focus on critical areas without requiring full visibility of all lower metal layer structures, thereby maintaining reliability assessment capability while working within miniaturized device constraints.
3Power
If current density increases in lower metal layers, then device functionality is maintained, but electromigration hotspots are generated causing potential IC failure
Solution Approach 1:
The patent applies preliminary action by performing EM analysis on cell output pins and lower metal layers before final device fabrication. This advance detection allows identification of EM hotspots caused by high current density in lower metal layers, enabling design modifications to prevent electromigration damage before it occurs, thereby maintaining device functionality while avoiding future failures.
Solution Approach 2:
The patent implements feedback by using EM analysis results from lower metal layers and cell output pins to guide design modifications. The feedback loop allows current density distributions to be evaluated and adjusted, enabling optimization of lower metal layer designs to reduce EM hotspots while maintaining required power delivery for device functionality.
Data Source
AI summary
A method for forming an integrated device includes following operations. It is provided a first circuit having a first connecting path in a metal line layer, a second connecting path, and a third connecting path. The second connecting path is electrically connected to a first connecting portion of the first connecting path in the metal line layer. The third connecting path is electrically coupled to a second connecting portion of the first connecting path in the metal line layer. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion in the metal line layer between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified to generate a second circuit when the third connecting portion induces EM phenomenon. The integrated device is generated according to the second circuit.