3D IC Clock Synchronization Using PLL Feedback Paths
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Solution Overview
Problem
Providing accurate clock signals in complex integrated circuit (IC) devices, particularly in three-dimensional (3D) IC devices with multiple stacked chips, is challenging due to time delays and jitter, which affect clock accuracy and latency.
Innovation Solution
Implementing a phase-locked loop (PLL) in one semiconductor die to generate a clock signal for another die, with a feedback path to compensate for communication channel delays, and using multiplexers to select between master and local clock signals, ensuring robust data transmission and minimal latency without the need for FIFO circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is transmitted between stacked semiconductor dies in a 3D IC device, then data transmission between dies is enabled, but time delays and jitter occur that degrade clock accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the transmitted clock signal is returned from the second semiconductor die to the first die. This returned clock signal is used to generate the clock signal for the first die, creating a closed-loop system that compensates for transmission delays and jitter, thereby maintaining clock accuracy despite the time delays inherent in inter-die communication
Solution Approach 2:
The patent introduces an intermediary approach by using the transmitted clock signal itself as the reference for generating the local clock signal. Instead of using separate independent clock sources that would suffer from synchronization issues, the system uses the actual transmitted clock signal (after it traverses the inter-die interface) as the basis for generating the receiving die's clock signal, effectively making the clock synchronization adaptive to the actual transmission conditions
2Reliability
If FIFO circuits are used to handle timing variations in clock signals, then data transmission robustness is improved, but area usage and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the need for FIFO (First-In-First-Out) buffering circuits by implementing a feedback-based clock generation system. By using the returned clock signal to generate the local clock signal, the system achieves automatic timing synchronization without requiring additional buffering infrastructure, thereby removing the area and power overhead associated with FIFO circuits while maintaining data transmission robustness
3Adaptability or versatility
If independent clock signals are used in each semiconductor die, then clock generation flexibility is improved, but clock synchronization between dies deteriorates
Solution Approach 1:
The patent merges the clock generation functions by making the clock signal in the first die dependent on the clock signal transmitted from and returned by the second die. This integration ensures that both dies operate from a unified clock reference that inherently accounts for transmission delays, achieving precise clock synchronization while maintaining the flexibility of independent die operation through the feedback mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances clock accuracy, provides extra timing margins, reduces power consumption, and minimizes area usage by eliminating the need for FIFO circuits, while maintaining robust input/output interfaces.
Implementation Method 1
a phase-locked loop (PLL) in one semiconductor die to generate a clock signal for another die, with a feedback path to compensate for communication channel delays
Data Source
AI summary
An integrated circuit (IC) device includes a first die including a first transmitting circuit, a first receiving circuit, and a first circuit. The first transmitting circuit transmits an output clock signal corresponding to a first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs, based on the input clock signal, a first signal corresponding to the input signal. The first circuit outputs, based on the first clock signal, a second signal corresponding to the first signal. The first circuit, in response to a first value of a first selection signal, outputs the second signal in response to a first edge of the first clock signal. The first circuit, in response to a second value different from the first value of the first selection signal, outputs the second signal in response to a second edge of the first clock signal.