3D-IC Concurrent Placement and Routing Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional approaches for optimizing 2D integrated circuit designs are suboptimal when applied to 3D integrated circuit designs, leading to inefficiencies in placement and routing due to limitations in 2D plane constraints, especially with the presence of hard macros that block direct paths and require excessive layer promotions, resulting in increased routing resources and congestion.
Innovation Solution
The method involves modeling multiple dies as a single 3D space, allowing cells to be placed and optimized across multiple dies without splitting the netlist, leveraging the larger solution space of 3D stacking to identify optimal placements and routing strategies, including the use of asymmetric routing layers and die-to-die interfaces for improved resource utilization and reduced congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 2D optimization approaches are applied to 3D-IC designs, then the design process remains simple and familiar, but routing resources increase and timing performance deteriorates due to 2D plane constraints
Solution Approach 1:
The patent transitions from 2D plane-based optimization to 3D space-based optimization by stacking multiple dies vertically. This dimensional change allows routing to occur in the vertical dimension through TSVs (through-silicon vias), enabling direct connections between dies without excessive layer promotions and reducing overall routing resource consumption while improving timing performance.
Solution Approach 2:
The patent implements a hierarchical optimization approach where 3D-IC placement and routing is decomposed into multiple 2D die-level optimizations. Each die is optimized individually in 2D space, then these optimized dies are stacked and connected in 3D space, combining the simplicity of 2D methods with the efficiency of 3D architecture.
2Adaptability or versatility
If hard macros are placed in 3D-IC designs, then functional integration improves, but routing congestion increases and direct paths are blocked requiring excessive layer promotions
Solution Approach 1:
The patent resolves routing congestion caused by hard macros by utilizing the vertical dimension. Instead of routing around macros in the 2D plane (which requires excessive layer promotions), the optimization routes signals vertically through TSVs to other dies, creating direct 3D paths that bypass macro blockages and reduce routing complexity.
Solution Approach 2:
The patent introduces TSVs (through-silicon vias) as intermediary connection structures between dies. These TSVs act as mediators that enable direct vertical routing paths, allowing signals to bypass hard macro blockages on individual dies and reducing the need for complex lateral routing around macros.
3Ease of manufacture
If multiple dies are optimized individually in 3D-IC, then each die can be optimized separately, but overall system optimization is suboptimal due to lack of concurrent consideration
Solution Approach 1:
The patent implements a nested optimization hierarchy where individual 2D die optimizations are performed first (inner level), then these results are integrated into a concurrent 3D multi-die optimization (outer level). This nested approach maintains the simplicity of individual die optimization while achieving superior overall system optimization through coordinated 3D placement and routing across all dies.
Solution Approach 2:
The patent segments the 3D-IC optimization problem into manageable 2D die-level subproblems that can be solved individually, then combines these segmented solutions through 3D stacking and TSV routing optimization. This segmentation allows use of efficient 2D algorithms while achieving 3D system-level optimization.
Data Source
AI summary
Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.