3D Monolithic IC Assembly for High-Bandwidth Die Coupling
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Solution Overview
Problem
Conventional IC packages face challenges in performance optimization due to manufacturing, thermal, and power delivery constraints, especially when integrating memory and compute dies, with communication between multiple dies being particularly challenging.
Innovation Solution
The implementation of 3D monolithic memory and compute functions, combined with nano-TSVs, die stitching, and glass carrier structures, allows for tight coupling and improved signal and power delivery, enhancing performance and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional IC packaging is used with multiple dies, then manufacturing and assembly are relatively simple, but performance optimization and communication between dies are challenging
Solution Approach 1:
The patent merges memory and compute dies into a single integrated 3D monolithic structure, eliminating the need for separate die assembly and interconnects. This integration resolves the contradiction by combining multiple functions into one manufacturable unit while achieving optimal performance through unified design and tight coupling of memory and compute elements.
Solution Approach 2:
The patent transitions from conventional 2D planar IC packaging to 3D vertical stacking with monolithic integration. This dimensional change enables superior performance by allowing direct vertical interconnects and tighter coupling between memory and compute elements, while maintaining manufacturing feasibility through adapted fabrication processes.
2Productivity
If 3D monolithic memory and compute functions are integrated, then bandwidth and signal delivery are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the 3D monolithic structure into distinct memory regions and compute regions with specialized interconnects. This segmentation allows optimized signal paths for high bandwidth while managing manufacturing complexity by dividing the fabrication process into manageable stages for different functional blocks.
Solution Approach 2:
The patent introduces intermediate buffer layers and control logic structures that mediate between memory and compute elements. These intermediaries enable high-speed communication and signal delivery while simplifying the manufacturing process by providing standardized interfaces and reducing direct complexity between opposing functional blocks.
3Quantity of substance
If multiple dies are stacked for increased capacity, then memory capacity increases, but thermal management and power delivery become challenging
Solution Approach 1:
The patent uses 3D vertical stacking to increase memory capacity while implementing thermal management through vertical heat dissipation paths. Heat can escape in the vertical dimension through the stack structure, and power delivery is optimized through vertical interconnects that reduce resistance and improve efficiency compared to lateral connections in conventional 2D packaging.
Data Source
AI summary
Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.