3D IC Memory Stack With Edge Pads for Thermal Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 2.5D/3D ICs face challenges in power, performance, area, and cost optimization due to bottom/top electrical interconnects, and insufficient heat dissipation from stacked DRAM memory semiconductor dies, leading to elevated chip temperatures.
Innovation Solution
The IC structure incorporates a first memory stack with semiconductor dies having edge pads on sidewalls connected via RDL structures, and includes thermal conductivity layers between adjacent dies to enhance heat dissipation, eliminating the need for through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used for electrical interconnects in stacked semiconductor dies, then vertical electrical connection is achieved, but manufacturing complexity and alignment difficulty increase severely
Solution Approach 1:
The patent transitions from vertical TSV interconnects to lateral edge pad interconnects. Edge pads are formed on the sidewalls of semiconductor dies and connect to adjacent dies through lateral bonding, eliminating the need for vertical through-silicon vias. This dimensional change from vertical to lateral interconnection resolves the manufacturing complexity and alignment difficulty of TSVs while maintaining reliable electrical connection.
2Productivity
If multiple DRAM memory semiconductor dies are stacked vertically to increase storage capacity, then integration density is improved, but heat dissipation capability deteriorates leading to elevated chip temperature
Solution Approach 1:
The patent arranges semiconductor dies in a horizontal stack configuration rather than vertical stacking. The dies are bonded side-by-side through edge pad connections, creating a lateral heat dissipation path. This dimensional reconfiguration allows heat to dissipate more effectively across the horizontal plane and through the bonding interfaces, resolving the heat dissipation problem associated with vertical stacking while maintaining high integration density.
Solution Approach 2:
The bonding interfaces between adjacent semiconductor dies serve as thermal pathways for heat dissipation. The lateral bonding structure creates intermediate thermal conduction paths through the bonding materials and edge pad regions, facilitating heat transfer from the active regions of each die to the surrounding structures. This intermediary heat dissipation mechanism effectively manages thermal load in high-density integrated structures.
3Reliability
If bottom/top electrical interconnects are used in 2.5D/3D IC packaging, then electrical connection is established, but power, performance, area and cost optimization becomes severely constrained
Solution Approach 1:
The patent employs lateral edge pad interconnects on the sidewalls of semiconductor dies, enabling flexible routing options that are not constrained by the fixed bottom/top interconnect architecture. This lateral connection approach allows designers to optimize power distribution, signal routing, and thermal management independently, providing greater adaptability for PPAC optimization while maintaining reliable electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design optimizes power, performance, and area while reducing costs by improving heat dissipation and reducing chip temperature, enhancing the efficiency of 2.5D/3D ICs.
Implementation Method 1
includes thermal conductivity layers between adjacent dies to enhance heat dissipation
Data Source
AI summary
An IC structure includes a first memory stack including a plurality of semiconductor die. The plurality of semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within a upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die.